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From cryptography to hardware: analyzing and protecting embedded Xilinx BRAM for cryptographic applications

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Abstract

The design of cryptographic applications needs special care. For instance, physical attacks like side-channel analysis (SCA) are able to recover the secret key, just by observing the activity of the computation, even for mathematically robust algorithms like AES. SCA considers the “leakage” of a well chosen intermediate variable correlated with the secret. Field programmable gate-arrays (FPGA) are often used for hardware implementations for low to medium volume productions or when flexibility is needed. They offer many possibilities for the computation, like small look-up tables (LUT) and embedded block memories (BRAM). Certain countermeasures can be deployed, like dual-rail logic or masking, to resist SCA on FPGA. However to design an effective countermeasure, it is of prime importance for a designer to know the main leakage sources of the device. In this paper, we analyze the leakage source of a Xilinx Virtex V FPGA by studying three different AES architectures. The analysis is based on real measurements by using specific leakage models of the sensitive variable, adapted to each architecture. Our results demonstrate that, BRAM which were considered to leak less traditionally, are found to be equally vulnerable if we change the attack target from address register to output latch. We also show that if the leakage model is known, simple countermeasures with only 16 % overhead can be deployed to overcome the leakage.

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Notes

  1. There are actually several kinds of “ghost peaks”. In this footnote, we give some examples from the SCA literature in order to disambiguate the different origins of wrong key guesses phenomenon. One example is when a high spurious correlation is obtained at an irrelevant position of the trace, which happens when there is a lot of noise and few traces traces available to estimate the CPA. This is illustrated for instance in Fig. 3 of [14] (it is labelled “noisy peak”). Another kind of ghost peak can appear because unrelated activity occurs simultaneously with that being exploited. This has been exemplified in [10, Section 5.1], on the example of a hardware DES. If the attacker applies a mono-bit difference-of-means, then the attack can fail, because the three ignored bits (assumed erroneously to be independent from the one under analysis) leak information that overcomes the target bit, and fools the attacker into finding an incorrect key. In this section, we account for another type of ghost peaks, that happen later in time than the primary leakage, for a leakage model that involves the sensitive variable used “transformed”.

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Acknowledgments

This research is partly supported by Strategic International Cooperative Program (Joint Research Type), Japan Science and Technology Agency (JST), and the French Agence Nationale pour la Recherche (ANR), via grant for project SPACES (Security evaluation of Physically Attacked Cryptoprocessors in Embedded Systems). The authors wish to thank Julien Francq and Antoine Wurker (EADS/Cassidian, Cyber Security Solutions Center) for insightful discussions about power attacks on AES and Grøstl [1].

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Authors and Affiliations

  1. Department COMELEC, Institut MINES-TELECOM/TELECOM-ParisTech, CNRS LTCI (UMR 5141), 37/39 rue Dareau, 75 014 , Paris, France

    Shivam Bhasin, Sylvain Guilley & Annelie Heuser

  2. Department COMELEC, Institut MINES-TELECOM/TELECOM- ParisTech, CNRS LTCI (UMR 5141), 46 rue Barrault, 75 634 , Paris Cedex 13, France

    Jean-Luc Danger

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  1. Shivam Bhasin
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Correspondence to Shivam Bhasin.

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Bhasin, S., Guilley, S., Heuser, A. et al. From cryptography to hardware: analyzing and protecting embedded Xilinx BRAM for cryptographic applications. J Cryptogr Eng 3, 213–225 (2013). https://doi.org/10.1007/s13389-013-0048-4

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