Abstract
Dozens of Advanced Encryption Standard (AES) implementations have been presented since AES was officially published by the National Institute of Standards and Technology in 2001. Many of these implementations have targeted FPGA platforms either for ASIC prototyping or as the destination hardware. Typically, these publications have comparative metrics to show how the proposed implementation compares to previously published work. Unfortunately, these metrics often present inaccurate comparisons. To date, these metrics have focused on area and speed, neglecting the third point of the hardware optimization triangle, power. As AES becomes more prolific and attractive for use in embedded devices, power considerations will be increasingly important. In this paper, we discuss the subtleties and qualities of metrics previously applied to FPGA AES publications. We then propose a power metric to generate a more complete, quantitative description of the quality of the implementation. The proposed metric is not specific to AES but has general FPGA design applicability. Finally, we present a comparison between four AES-256 implementations that demonstrates the inconsistent conclusions drawn when various metrics are used.
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Federal Information Processing Standards Publication 197—Announcing the ADVANCED ENCRYPTION STANDARD (AES), National Institute of Standards and Technology (NIST), November 2001 (2001)
Chodowiec, P., Gaj, K.: Very compact FPGA implementation of the aes algorithm. In: CHES, pp. 319–333 (2003)
Rouvroy, G., Standaert, F.X., Quisquater, J.J., Legat, J.D.: Compact and efficient encryption/decryption module for FPGA implementation of the aes rijndael very well suited for small embedded applications. In: International Conference on Information Technology: Coding and Computing, 2004. Proceedings of ITCC 2004, vol. 2, april 2004, pp. 583–587 (2004)
Standaert, F.X., Rouvroy, G., Quisquater, J.J., Legat, J.D.: Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs, pp. 334–350 (2003)
Zambreno, J., Nguyen, D., Choudhary, A.: Exploring area/delay tradeoffs in an aes FPGA implementation. In: Proceedings of the 14th Annual International Conference on Field-Programmable Logic and Applications (FPL 04), pp. 575–585. Springer, Berlin (2004)
Oswald, E.: State of the art in hardware architectures. In: Technical Report, ECRYPTEuropean Network of Excellence in Cryptology (2005)
Chang, C.J., Huang, C.W., Chang, K.H., Chen, Y.C., Hsieh, C.C.: High throughput 32-bit aes implementation in FPGA. In: IEEE Asia Pacific Conference on Circuits and Systems, 2008. APCCAS 2008, 30 2008–Dec. 3, pp. 1806–1809 (2008)
Fan C.P., Hwang, J.K.: Implementations of high throughput sequential and fully pipelined aes processors on FPGA. In: Intelligent Signal Processing and Communication Systems, 2007. ISPACS 2007. International Symposium on, 28 2007–Dec. 1, pp. 353–356 (2007)
Qu, S., Shou, G., Hu, Y., Guo, Z., Qian, Z.: High throughput, pipelined implementation of aes on FPGA. In: International Symposium on Information Engineering and Electronic Commerce, 2009. IEEC 09, May 2009, pp. 542–545 (2009)
Rizk, M., Morsy, M.: Optimized area and optimized speed hardware implementations of AES on FPGA. In: 2nd International Design and Test Workshop, 2007. IDT 2007, Dec. 2007, pp. 207–217
Verbauwhede, I., Schaumont, P., Kuo, H.: Design and performance testing of a 2.29-gb/s rijndael processor. IEEE J. Solid-State Circuits 38(3); 569–572 (2003)
Dongara, P., Vijaykumar, T.: Accelerating private-key cryptography via multithreading on symmetric multiprocessors. In: 2003 IEEE International Symposium on Performance Analysis of Systems and Software, 2003. ISPASS, March 2003, pp. 58–69 (2003)
Elbirt, A., Yip, W., Chetwynd, B., Paar, C.: An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalists. In: The Third Advanced Encryption Standard Candidate Conference, 2000. AES3 2000 (2000)
Xilinx: Virtex-6 Family Overview, January 2012, dS150 (2012)
Xilinx: Virtex-4 Family Overview, August 2010, dS112 (2010)
Jarvinen, K., Tommiska, M., Skytta, J.: Comparative survey of high-performance cryptographic algorithm implementations on FPGAs. IEE Proc. Inf. Secur. 152(1), 3–12 (2005)
Saggese, G., Mazzeo, A., Mazzocca, N., Strollo, A.: An FPGA-based performance analysis of the unrolling, tiling, and pipelining of the AES algorithm. In: Cheung, P.Y.K., Constantinides, G. (eds.) Field Programmable Logic and Application. Lecture Notes in Computer Science, vol. 2778, pp. 292–302. Springer, Berlin (2003). doi:10.1007/978-3-540-45234-829
Good, T., Benaissa, M.: AES on FPGA from the fastest to the smallest. In: Rao, J., Sunar, B. (eds.) Cryptographic Hardware and Embedded Systems (CHES) 2005. Lecture Notes in Computer Science, vol. 3659, pp. 427–440. Springer, Berlin (2005). doi:10.1007/11545262
Huang, C.W., Chang, C.J., Lin, M.Y., Tai, H.Y.: The FPGA implementation of 128-bits aes algorithmbased on four 32-bits parallel operation. In: The First International Symposium on Data, Privacy, and E-Commerce, 2007. ISDPE 2007, Nov. 2007, pp. 462–464 (2007)
Hodjat, A., Verbauwhede, I.: A 21.54 gbits/s fully pipelined aes processor on FPGA. In: 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2004. FCCM 2004, April 2004, pp. 308–309 (2004)
Horowitz, M., Indermaur, T., Gonzalez, R.: Low-power digital design. In: IEEE Symposium on Low Power Electronics, 1994. Digest of Technical Papers, Oct 1994, p. 811 (1994)
Didla, S., Ault, A., Bagchi, S.: Optimizing aes for embedded devices and wireless sensor networks. In: Proceedings of the 4th International Conference on Testbeds and Research Infrastructures for the Development of Networks and Communities. TridentCom 08. ICST, Brussels, Belgium, Belgium: ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), 2008, pp. 4:14:10 (2008)
Gupta, A., Ahmad, A., Sharif, M., Amira, A.: Rapid prototyping of aes encryption for wireless communication system on FPGA. In: 2011 IEEE 15th International Symposium on Consumer Electronics (ISCE), June 2011, pp. 571–575 (2011)
Ghaznavi, S., Gebotys, C., Elbaz, R.: Efficient technique for the FPGA implementation of the aes mixcolumns transformation. In: International Conference on Reconfigurable Computing and FPGAs, 2009. ReConFig 09, Dec. 2009, pp. 219–224 (2009)
Ruschival, T.: (2010, March) Avalon aes ecb-core (128, 192, 256 bit). OpenCores. http://opencores.org/project,avs_aes
Gbur, J.: (2011, Nov) AES core modules. OpenCores. http://opencores.org/project,aes128192256
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Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000.
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Templin, J.R., Hamlet, J.R. A new power-aware FPGA design metric. J Cryptogr Eng 5, 1–11 (2015). https://doi.org/10.1007/s13389-013-0060-8
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DOI: https://doi.org/10.1007/s13389-013-0060-8