Skip to main content
SpringerLink
Log in

A new method for enhancing variety and maintaining reliability of PUF responses and its evaluation on ASICs

  • Regular Paper
  • Published:
Journal of Cryptographic Engineering Aims and scope Submit manuscript

Abstract

Physically unclonable functions (PUFs) are expected to provide a breakthrough in anti-counterfeiting devices for secure ID generation and authentication, etc. Factory-manufactured PUFs are generally more secure if the number of outputs (the variety of responses) is larger (e.g., a 256-bit full-entropy response is more secure than a 128-bit response). In Yamamoto et al. (J Cryptogr Eng 3(4):197–211, 2013), we presented a latch-based PUF structure, which enhances the variety of responses by utilizing the location information of the RS (Reset-Set) latches outputting random numbers. We confirmed the effectiveness of this method using two kinds of different Xilinx FPGA chips: Spartan-3E and Spartan-6. In this paper, we propose a novel method of further enhancing the variety of responses while maintaining the reliability of responses, i.e., consistency over repeated measurements. The core idea in this method is to effectively utilize the information on the proportion of ‘1’s in the random number sequence output by the RS latches. This proportion information is determined during the manufacturing process, making it relatively stable and reliable once PUFs are manufactured. We estimated the variety of responses generated by the PUFs to which the proposed method was applied. According to our experiment with 73 ASIC chips fabricated by a 0.18-\(\upmu \)m CMOS process, latch-based PUFs with 256 RS latches can improve the variety of responses to as much as \(2^{379}\). This is much larger than \(2^{220}\) for conventional methods, and \(2^{314}\) for our previous method presented in Yamamoto et al., J Cryptogr Eng 3(4):197–211, 2013). The average error rate (reliability) of responses is only 0.064 when both temperature and voltage are changed to \(-20 \sim 60^\circ \)C and \(1.80 \pm 0.15\mathrm{V}\), respectively. Our proposed PUF enhances the variety of responses dramatically while maintaining reliability.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9

Similar content being viewed by others

References

  1. Armknecht, F., Maes, R., Sadeghi, A.R., Sunar, B., Tuyls, P.: Memory leakage-resilient encryption based on physically unclonable functions. In: Sadeghi, A.R., Naccache, D. (eds.) Towards Hardware-Intrinsic Security, Information Security and Cryptography, pp. 135–164. Springer, Berlin (2010)

    Chapter  Google Scholar 

  2. van den Berg, R., Skoric, B., van der Leest, V.: Bias-based modeling and entropy analysis of PUFs. In: Proceedings of the 3rd International Workshop on Trustworthy Embedded Devices, TrustED ‘13, pp. 13–20. ACM (2013)

  3. Bogdanov, A., Knezevic, M., Leander, G., Toz, D., Varici, K., Verbauwhede, I.: Spongent: the design space of lightweight cryptographic hashing. IEEE Trans. Comput. 62(10), 2041–2053 (2013)

    Article  MathSciNet  Google Scholar 

  4. Bösch, C., Guajardo, J., Sadeghi, A.R., Shokrollahi, J., Tuyls, P.: Efficient helper data key extractor on FPGAs. In: CHES, pp. 181–197 (2008)

  5. Briais, S., Cioranesco, J.M., Danger, J.L., Guilley, S., Naccache, D., Porteboeuf, T.: Random active shield. In: Fault Diagnosis and Tolerance in Cryptography (FDTC), 2012 Workshop on, pp. 103–113 (2012)

  6. Dodis, Y., Ostrovsky, R., Reyzin, L., Smith, A.: Fuzzy extractors: How to generate strong keys from biometrics and other noisy data. SIAM J. Comput. 38, 97–139 (2008)

    Article  MathSciNet  MATH  Google Scholar 

  7. Gassend, B., Clarke, D., van Dijk, M., Devadas, S.: Silicon physical random functions. In: Proceedings of CCS pp. 148–160 (2002)

  8. Gassend, B., Clarke, D., Lim, D., van Dijk, M., Devadas, S.: Identification and authentication of integrated circuits. In: Concurrency and computation: practice and experiences., pp. 1077–1098 (2004)

  9. Gorman, C.: Counterfeit chips on the rise. Spectr. IEEE 49(6), 16–17 (2012)

    Article  Google Scholar 

  10. Guajardo, J., Kumar, S.S., Schrijen, G.J., Tuyls, P.: FPGA intrinsic PUFs and their use for IP protection. CHES 2007, 63–80 (2007)

  11. Hata, H., Ichikawa, S.: FPGA implementation of metastability-based true random number generator. IEICE Trans. 95(D–2), 426–436 (2012)

    Google Scholar 

  12. Helfmeier, C., Boit, C., Nedospasov, D., Seifert, J.P.: Cloning physically unclonable functions. In: HOST (2013)

  13. Holcomb, D.E., Burleson, W.P., Fu, K.: Initial SRAM state as a fingerprint and source of true random numbers for RFID tags. In: Proceedings of the Conference on RFID Security (2007)

  14. Holcomb, D.E., Rahmati, A., Salajegheh, M., Burleson, W.P., Fu, K.: DRV-fingerprinting: using data retention voltage of SRAM cells for chip identification. In: RFIDSec, pp. 165–179 (2012)

  15. Ignatenko, T., Schrijen, G.J., Skoric, B., Tuyls, P., Willems, F.: Estimating the secrecy-rate of physical unclonable functions with the context-tree weighting method. In: Information Theory, 2006 IEEE International Symposium on, pp. 499–503 (2006)

  16. Krishna, A.R., Narasimhan, S., Wang, X., Bhunia, S.: Mecca: a robust low-overhead PUF using embedded memory array. In: CHES, pp. 407–420 (2011)

  17. Kumar, S.S., Guajardo, J., Maes, R., Schrijen, G.J., Tuyls, P.: Extended abstract: the Butterfly PUF: protecting IP on every FPGA. In: HOST, pp. 67–70 (2008)

  18. Lee, J.W., Lim, D., Gassend, B., Suh, G.E., van Dijk, M., S.Devadas: A technique to build a secret key in integrated circuits for identification and authentication applications. In: Proceedings of the IEEE VLSI Circuits Symposium, pp. 176–179 (2004)

  19. Ltd., F.S.: CS86 technology. http://www.fujitsu.com/downloads/MICRO/fma/pdf/e620209_CS86_ASIC.pdf

  20. Maes, R., Tuyls, P., Verbauwhede, I.: Intrinsic PUFs from flip-flops on reconfigurable devices. In: 3rd Benelux Workshop on Information and system security (WISSec 2008), p. 17 (2008)

  21. Maes, R., Tuyls, P., Verbauwhede, I.: Low-overhead implementation of a soft decision helper data algorithm for SRAM PUFs. CHES pp. 332–347 (2009)

  22. Maes, R., Verbauwhede, I.: Physically unclonable functions: a study on the state of the art and future research directions. In: Towards hardware intrinsic security: foundation and practice, pp. 3–37. Springer (2010)

  23. Maiti, A., Gunreddy, V., Schaumont, P.: A systematic method to evaluate and compare the performance of physical unclonable functions. In: Embedded systems design with FPGAs, pp. 245–267. Springer, New York (2013)

  24. Manyika, J., Chui, M., Brown, B., Bughin, J., Dobbs, R., Roxburgh, C., Byers, A.H.: Big data: the next frontier for innovation, competition, and productivity. Tech. rep, McKinsey Global Institute (2011)

  25. Maurer, U.M.: Secret key agreement by public discussion from common information. IEEE Trans Inf Theory 39(3), 733–742 (1993)

    Article  MATH  Google Scholar 

  26. Pappu, R.S.: Physical one-way functions. Ph. D. thesis, Massachusetts Institute of Technology (2001)

  27. Rührmair, U., Sehnke, F., Sölter, J., Dror, G., Devadas, S., Schmidhuber, J.: Modeling attacks on physical unclonable functions. In: Proceedings of the 17th ACM conference on Computer and communications security, CCS 2010, pp. 237–249 (2010)

  28. Simons, P., van der Sluis, E., van der Leest, V.: Buskeeper PUFs, a promising alternative to D Flip-Flop PUFs. In: Hardware-Oriented Security and Trust (HOST), 2012 IEEE International Symposium on, pp. 7–12 (2012)

  29. Su, Y., Holleman, J., Otis, B.: A 1.6pJ/bit 96% stable chip-ID generating circuit using process variations. In: IEEE International Solid-State Circuits Conference—ISSCC 2007. IEEE, pp. 406–611 (2007)

  30. Su, Y., Holleman, J., Otis, B.P.: A digital 1.6pJ/bit chip identification circuit using process variations. Solid-State Circuits IEEE J. 43(1), 69–77 (2008)

  31. Suh, G.E., Devadas, S.: Physical unclonable functions for device authentication and secret key generation. In: Proceedings of DAC pp. 9–14 (2007)

  32. Torrance, R., James, D.: The state-of-the-art in IC reverse engineering. In: CHES, pp. 363–381 (2009)

  33. Tuyls, P., Schrijen, G.J., Skoric, B., van Geloven, J., Verhaegh, N., Wolters, R.: Read-proof hardware from protective coatings. In: CHES, pp. 369–383 (2006)

  34. Xilinx: Spartan-3E starter kit board. http://www.xilinx.com/products/boards-and-kits/hw-spar3e-sk-us-g.html

  35. Yamamoto, D., Sakiyama, K., Iwamoto, M., Ohta, K., Takenaka, M., Itoh, K.: Variety enhancement of PUF responses using the locations of random outputting RS latches. J Cryptogr Eng 3(4), 197–211 (2013)

Download references

Author information

Authors and Affiliations

  1. Fujitsu Laboratories Ltd, 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa, 211-8588, Japan

    Dai Yamamoto, Masahiko Takenaka, Kouichi Itoh & Naoya Torii

  2. The University of Electro-Communications, 1-5-1, Chofugaoka, Chofu, Tokyo, 182-8585, Japan

    Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto & Kazuo Ohta

Authors
  1. Dai Yamamoto
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Kazuo Sakiyama
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Mitsugu Iwamoto
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Kazuo Ohta
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Masahiko Takenaka
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Kouichi Itoh
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. Naoya Torii
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Dai Yamamoto.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Yamamoto, D., Sakiyama, K., Iwamoto, M. et al. A new method for enhancing variety and maintaining reliability of PUF responses and its evaluation on ASICs. J Cryptogr Eng 5, 187–199 (2015). https://doi.org/10.1007/s13389-014-0091-9

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s13389-014-0091-9

Keywords

Search

Navigation