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Low area-time complexity point multiplication architecture for ECC over GF(\(2^{\textrm{m}}\)) using polynomial basis

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Abstract

In the present day, billions of devices communicate over the wireless networks. The massive information transmitted over open ended, and unsecured Internet architecture results in eavesdropping of private, sensitive and confidential information. Therefore, it is necessary to incorporate some data encryption techniques while communicating any sensitive information. Public key cryptography is one of the widely used data encryption technique, and elliptic curve cryptography (ECC) is the most-sought after public key cryptographic algorithm. The efficiency of ECC depends on a series of hierarchical finite field operations, and point multiplication is one of the most time-critical and resource-consuming ECC operation. Point multiplication involves a substantial number of multiplications, additions and inversion operations over finite fields of higher orders. In this article, we present a point multiplication architecture developed for a modified Montgomery-ladder algorithm. A digit-serial multiplier is employed to perform multiplication in the realization of the modified Montgomery-ladder algorithm. The area and time complexities of the proposed elliptic curve point multiplication (ECPM) architecture are computed for irreducible pentanomial GF(2\(^{163}\)) and irreducible trinomial GF(2\(^{233}\)) targeting Virtex-5(XC5VLX110) FPGA and compared with the similar architectures available in the literature.

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References

  1. Yang, Y., Wu, L., Yin, G., Li, L., Zhao, H.: A survey on security and privacy issues in internet-of-things. IEEE Internet Things J. 4(5), 1250–1258 (2017)

    Article  Google Scholar 

  2. Koblitz, N.: Elliptic curve cryptosystems. Math. Comput. 48(177), 203–209 (1987). https://doi.org/10.1090/S0025-5718-1987-0866109-5

    Article  MathSciNet  MATH  Google Scholar 

  3. Miller, V.S.: Use of Elliptic Curves in Cryptography. In: CRYPTO 1985 Conference on the Theory and Application of Cryptographic Techniques; Springer, Berlin, Heidelberg; pp. 417-426 (1986)

  4. Hankerson, D., Menezes, A.J., Vanstone, S.: Guide to elliptic curve cryptography. Springer, Secaucus, NJ, USA (2003)

    MATH  Google Scholar 

  5. Sakiyama, K., Batina, L., Preneel, B., Verbauwhede, I.: Superscalar coprocessor for high-speed curve-based cryptography. In: International Workshop on Cryptographic Hardware and Embedded Systems: 10, pp. 415–429. Springer, Berlin, Heidelberg (2006)

  6. Chelton, W.N., Benaissa, M.: Fast elliptic curve cryptography on FPGA. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16(2), 198–205 (2008). https://doi.org/10.1109/TVLSI.2007.912228

    Article  Google Scholar 

  7. Kim, C.H., Kwon, S., Hong, C.P.: FPGA implementation of high performance elliptic curve cryptographic processor over GF(\(2^{163}\)). J. Syst. Architect. 54(10), 893–900 (2008). https://doi.org/10.1016/j.sysarc.2008.03.005

    Article  Google Scholar 

  8. Hasan, M., Ansari, B.: High-performance architecture of elliptic curve scalar multiplication. IEEE Trans. Comput. 57(11), 1443–1453 (2008). https://doi.org/10.1109/TC.2008.133

    Article  MathSciNet  MATH  Google Scholar 

  9. Azarderakhsh, R., Reyhani-Masoleh, A.: Efficient FPGA implementations of point multiplication on binary Edwards and generalized Hessian curves using Gaussian normal basis. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20(8), 1453–66 (2011)

    Article  Google Scholar 

  10. C. Rebeiro, S.S. Roy, D., Mukhopadhyay: “Pushing the limits of high-speed GF(2m) elliptic curve scalar multiplication on FPGAs,” in Proc. Int. Workshop CHES, pp. 494–511 (2012)

  11. Roy, S.S., Rebeiro, C., Mukhopadhyay, D.: Theoretical modeling of elliptic curve scalar multiplier on LUT-based FPGAs for area and speed. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21(5), 901–9 (2012)

    Article  Google Scholar 

  12. Sutter, G.D., Deschamps, J., Imana, J.L.: Efficient elliptic curve point multiplication using digit-serial binary field operations. IEEE Trans. Ind. Electron. 60(1), 217–225 (2013). https://doi.org/10.1109/TIE.2012.2186104

    Article  Google Scholar 

  13. Nguyen, T.T., Lee, H.: Efficient algorithm and architecture for elliptic curve cryptographic processor. J. Semicond. Technol. Sci. 16(1), 118–125 (2016)

    Article  Google Scholar 

  14. Khan, Z.H., Benaissa, M.: High-speed and low-latency ECC processor implementation over GF(2m) on FPGA. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(1), 165–176 (2017)

    Article  Google Scholar 

  15. Salarifard, R., Bayat-Sarmadi, S., Mosanaei-Boorani, H.: A low-latency and low-complexity point-multiplication in ECC. IEEE Transactions on Circuits and Systems I: Regular Papers. 65(9), 2869–77 (2018)

    Article  Google Scholar 

  16. Li, J., Li, Z., Cao, S., Zhang, J., Wang, W.: Speed-oriented architecture for binary field point multiplication on elliptic curves. IEEE Access 7, 32048–60 (2019)

    Article  Google Scholar 

  17. Wenger, E., Hutter, M.: Exploring the design space of prime field vs. binary field ECC-hardware implementations. In: Nordic Conference on Secure IT Systems 2011 Oct 26 (pp. 256-271). Springer, Berlin, Heidelberg

  18. Lopez, J., Dahab, R.: Improved algorithms for elliptic curve arithmetic in GF(\(2^{n}\)). In: Proceedings of the Selected Areas in Cryptography (SAC); Springer, Berlin, Heidelberg; pp. 201-212 (1998)

  19. Rodríguez, H.F., Saqib, N.A., Díaz, P.A., Koc, C.K.: Signals and communication technology: cryptographic algorithms on reconfigurable hardware. Springer Science Business Media, Berlin, Heidelberg (2007)

    Google Scholar 

  20. Lopez, J., Dahab, R.: Fast Multiplication on Elliptic Curves Over GF(\({2}^m\)) without precomputation. In: CHES 1999 Cryptographic Hardware and Embedded Systems Conference; Springer, Berlin, Heidelberg;S pp. 316-327 (1999)

  21. Rashidi, B.: A survey on hardware implementations of elliptic curve cryptosystems. Electrical Engineering and Systems Science(ESSS). Cornell University, 2017. arXiv preprint arXiv:1710.08336

  22. Montgomery, P.L.: Speeding the Pollard and elliptic curve methods of factorization. Math. Comput. 48(177), 243–64 (1987)

    Article  MathSciNet  MATH  Google Scholar 

  23. Li, L., Li, S.: High-performance pipelined architecture of elliptic curve scalar multiplication over GF(\({2}^{m}\)). IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24(4), 1223–1232 (2016). https://doi.org/10.1109/TVLSI.2015.2453360

    Article  Google Scholar 

  24. Itoh, T., Tsujii: A fast algorithm for computing multiplicative inverses in GF(\(2^{m}\)) using normal bases. Inf. Comput. 78(3), 171–177 (1988). https://doi.org/10.1016/0890-5401(88)90024-7

  25. Nadikuda, P.K., Boppana, L.: An area-efficient architecture for finite field inversion over GF (\(2^ m\)) using polynomial basis. Microprocessors Microsyst. 22, 104439 (2022)

    Article  Google Scholar 

  26. Zakerolhosseini, A., Nikooghadam, M.: Low-power and high-speed design of a versatile bit-serial multiplier in finite fields GF (2m). IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 46(2), 211–7 (2013)

    Google Scholar 

  27. Meher, P.K.: Systolic and non-systolic scalable modular designs of finite field multipliers for Reed-Solomon codec. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17(6), 747–57 (2009)

    Article  Google Scholar 

  28. Rashidi, B., Farashahi, R.R., Sayedi, S.M.: High-speed and pipelined finite field bit-parallel multiplier over GF (2 m) for elliptic curve cryptosystems. In2014 11th International ISC Conference on Information Security and Cryptology 2014 Sep 3 (pp. 15-20). IEEE

  29. Rashidi, B., Sayedi, S.M., Farashahi, R.R.: High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems. Microelectron. J. 52, 49–65 (2016)

    Article  Google Scholar 

  30. Fournaris, A.P., Sklavos, N., Koulamas, C.: A high speed scalar multiplier for binary edwards curves. InProceedings of the Third Workshop on Cryptography and Security in Computing Systems Jan 20 (pp. 41-44) (2016)

  31. Parrilla, L., Álvarez-Bermejo, J.A., Castillo, E., López-Ramos, J.A., Morales-Santos, D.P., García, A.: Elliptic curve cryptography hardware accelerator for high-performance secure servers. J. Supercomput. 75(3), 1107–22 (2019)

    Article  Google Scholar 

  32. Harb, S., Jarrah, M.: FPGA implementation of the ECC over GF (2m) for small embedded applications. ACM Trans. Embedded Comput. Syst. (TECS) 18(2), 1–9 (2019)

    Article  Google Scholar 

  33. Xiong, X., Fan, H.: GF (2 n) bit-parallel squarer using generalised polynomial basis for new class of irreducible pentanomials. Electron. Lett. 50(9), 655–7 (2014)

    Article  Google Scholar 

  34. Song, L., Parhi, K.K.: Low-energy digit-serial/parallel finite field multipliers. J. VLSI Signal Process. Syst. Signal Image Video Technol. 19(2), 149–66 (1998)

    Article  Google Scholar 

  35. Kim, C.H., Hong, C.P., Kwon, S.: A digit-serial multiplier for finite field GF (2/sup m/). IEEE Trans. Very Large Scale Integr.(VLSI) Syst. 13(4), 476–83 (2005)

    Article  Google Scholar 

  36. Tang, W., Wu, H., Ahmadi, M.: VLSI implementation of bit-parallel word-serial multiplier in GF (2/sup 233/). InThe 3rd International IEEE-NEWCAS Conference, 2005. 2005 Jun 22 (pp. 399-402). IEEE

  37. Kumar, S., Wollinger, T., Paar, C.: Optimum digit serial GF (\(2^ m\)) multipliers for curve-based cryptography. IEEE Trans. Comput. 55(10), 1306–11 (2006)

    Article  Google Scholar 

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Authors and Affiliations

  1. Electronics and Communication Engineering, National Institute of Technology, Warangal, Telangana, 506001, India

    Pradeep Kumar Goud Nadikuda & Lakshmi Boppana

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  1. Pradeep Kumar Goud Nadikuda
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  2. Lakshmi Boppana
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Contributions

All authors contributed to the study conception and design. Material preparation, data collection and analysis were performed by all the authors. The first draft of the manuscript was written by PKG Nadikuda, and all authors commented on previous versions of the manuscript. All authors read and approved the final manuscript.

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Correspondence to Pradeep Kumar Goud Nadikuda.

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Nadikuda, P.K.G., Boppana, L. Low area-time complexity point multiplication architecture for ECC over GF(\(2^{\textrm{m}}\)) using polynomial basis. J Cryptogr Eng 13, 107–123 (2023). https://doi.org/10.1007/s13389-022-00302-0

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