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Trust Filter: Runtime Hardware Trojan Detection in Behavioral MPSoCs

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Abstract

This work introduces a runtime system level method to detect hardware Trojan in third party behavioral intellectual properties (3PBIPs). Most of the HW Trojan detection techniques either rely on golden Trojan-free (trusted) models, which are compared to the suspected model, or source IPs with the same functionality from different vendors. In the case of BIPs, this is extremely hard, as it is a market still in its infancy. Moreover, it is very difficult to find HW Trojan at the system level as the trigger condition might be visible only when the system is fully functional. Thus, this work proposes the inclusion of a small HW Trojan detection circuit called trust filters to detect HW Trojan at runtime. With the help of cycle-accurate simulation model, it is possible to fine tune these filters so that the overall system has no performance degradation. This can be achieved by exploiting the slack time between the time that a slave returns the data to the master and the time that the master sends new data to the slave. The advantages of using C-based design are multi-fold: (i) It allows the generation of fast cycle-accurate models to measure the exact slack of each BIP mapped as a loosely coupled Hardware Accelerator (HWAcc) slave and (ii) its ability to build the complete SoC using synthesizable Application Programming Interfaces (APIs) and hence allowing the fine tuning of these trust filters. Experimental results show that our proposed architecture is very efficient leading to no performance penalties in many cases and has very small area overhead.

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Notes

  1. Reference output and the golden IPs should not be confused. The reference outputs are the set of test vectors provided by the IP vendor for the preliminary verification of the IP. Golden model is a complete IP to which any IP of the same functionality can be compared.

  2. This work makes indistinguishable use of the terms HWAccs, slave, and BIP to designate the computationally intensive task synthesized using HLS.

References

  1. International technology roadmap for semiconductors, http://www.itrs.net/reports.html http://www.itrs.net/reports.html, accessed 25th December 2015

  2. Coussy P, Morawiec A (2008) High-level synthesis - from algorithm to digital circuit. Springer chapter 7, pp 113–127

  3. Cao Y, Chang CH, Chen S (2014) A cluster-based distributed active current sensing circuit for hardware Trojan detection. IEEE Trans Inf Forensics Secur 9(12):2220–2231

    Article  Google Scholar 

  4. Karri M, Rajendran J, Rosenfeld K, Tehranipoor M (2010) Trustworthy hardware: identifying and classifying hardware Trojans. IEEE Comput 43(10):39–46

    Article  Google Scholar 

  5. Bhunia S, Abramovici M, Agarwal D et al (2013) Protection against hardware Trojan attacks: towards a comprehensive solution. IEEE Tran Design Test 30(3):6–17

    Article  Google Scholar 

  6. Bhunia S, Hsiao M, Banga M et al (2014) Hardware Trojan attacks: threat analysis and countermeasures. Proc IEEE 102(8):1229–1247

    Article  Google Scholar 

  7. Banga M, Hsiao M (2010) Trusted RTL: Trojan detection methodology in pre-silicon designs, IEEE international symposium on hardware oriented security and trust (HOST 2010), Anaheim, pp 56–59

  8. Yang Jou J, Nan Jimmy Liu C (1999) Coverage analysis techniques for HDL design validation Proceedings asia pacific CHip design languages (APCHDL 1999) Fukuoka, pp 48–55

    Google Scholar 

  9. Love E, Jin Y, Markis Y (2012) Proof-carrying hardware intellectual property: a pathway to trusted module acquisition. IEEE Trans Inf Forensics Secur 7(1):25–40

    Article  Google Scholar 

  10. Waksman A, Sethumadhavan S (2011) Silencing hardware backdoors, IEEE symposium on security and privacy (SP 2011), Berkley, pp 22–25

  11. Beaumont M, Hopkins B, Newby T (2012) SAFER PATH: security architecture using fragmented execution and replication for protection against trojaned hardware Design, automation & test in Europe conference & exhibition (DATE2012), Dresden, pp 1000–1005

    Google Scholar 

  12. Rajendran J, Zhang H, Sinanoglu O et al (2013) High-level synthesis for security and trust IEEE online testing symposium (IOLTS 2013), Chania, pp 232–233

    Chapter  Google Scholar 

  13. Cui X, Ma K, Shi L et al (2014) High-level synthesis for run-time hardware Trojan detection and recovery Design automation conference (DAC 2014), San Francisco, pp 1–6

    Google Scholar 

  14. Waksman A, Suozzo M, Sethumadhavan S (2013) FANCI: identification of stealthy malicious logic using boolean functional Analysis Proceedings of ACM SIGSAC conference on computer communications security, New York, pp 697–708

    Google Scholar 

  15. Zhang J, Yuan F, Wei L et al (2013) VeriTrust: verification for hardware trust Design automation conference (DAC 2013), Austin, pp 1–8

    Google Scholar 

  16. Zhang J, Yuan F, Wei L et al (2015) VeriTrust: verification for hardware trust. IEEE Trans Comput Aided Des Integr Circuits Syst 34(7):1148–1161

    Article  Google Scholar 

  17. Liu C, Rajendran J, Yang C et al (2013) Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling IEEE international symosium on defect and fault tolerance in VLSI and nanotechnology systems (DFT 2013), New York, pp 101–106

    Chapter  Google Scholar 

  18. NEC CyberWorkBench, www.cyberworkbench.com, accessed 5 June 2016

  19. Carrion Schafer B, Mahapatra A (2014) S2CBench: synthesizable SystemC benchmark suite for high-level synthesis. IEEE Embed Syst Lett 6(3):53–56

    Article  Google Scholar 

  20. Trust Hub, https://www.trust-hub.org/resources/benchmarks, accessed 8 September 2016

Download references

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Correspondence to Nandeesha Veeranna.

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Veeranna, N., Schafer, B.C. Trust Filter: Runtime Hardware Trojan Detection in Behavioral MPSoCs. J Hardw Syst Secur 1, 56–67 (2017). https://doi.org/10.1007/s41635-017-0005-2

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