Abstract
This paper reviews a developed integrated circuit (IC) decomposition workflow that can be leveraged for extracting design files and performing advanced verification and validation techniques on fabricated chips. In this work, a commercial 130-nm microcontroller is delayered and imaged to recreate the full design stack-up. Using MicroNet’s Pix2Net, the features for each layer are extracted allowing a GDSII file to be generated and design netlists for target components to be recovered. The full decomposition process is executed on both the read only memory (ROM) array and universal serial communications interface (USCI) of the microcontroller to recover the layout GDSII and circuit netlist. A single-precision floating point unit (FPU) test article is used to incorporate a spectrum of error types into the design layout, thus creating a set of test articles with obfuscated errors. Once the netlists for each of the modified designs are extracted, formal verification techniques are applied to each netlist, thus illuminating the errors originally inserted into the layout. The extracted netlists are then converted into register transfer level (RTL) representations and simulated with the original design verification testbench.
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Funding
The work presented in this paper was sponsored by the Air Force Research Laboratory in Dayton, OH. Approved for public release (approval ID: 88ABW-2019-1048).
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Kimura, A., Scholl, J., Schaffranek, J. et al. A Decomposition Workflow for Integrated Circuit Verification and Validation. J Hardw Syst Secur 4, 34–43 (2020). https://doi.org/10.1007/s41635-019-00086-6
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DOI: https://doi.org/10.1007/s41635-019-00086-6