Physical Layer Encryption for Wireless OFDM Communication Systems

Abstract

Our everyday lives are impacted by the widespread adoption of wireless communication systems integral to residential, industrial, and commercial settings. Devices must be secure and reliable to support the emergence of large scale heterogeneous networks. Higher layer encryption techniques such as Wi-Fi Protected Access (WPA/WPA2) are vulnerable to threats, including even the latest WPA3 release. Physical layer security leverages existing components of the physical or PHY layer to provide a low-complexity solution appropriate for wireless devices. This work presents a PHY layer encryption technique based on frequency induction for Orthogonal Frequency Division Multiplexing (OFDM) signals to increase security against eavesdroppers. The secure transceiver consists of a key to frequency shift mapper, encryption module, and modified synchronizer for decryption. The system has been implemented on a Virtex-7 FPGA. The additional hardware overhead incurred on the Virtex-7 for both the transmitter and the receiver is low. Both simulation and hardware evaluation results demonstrate that the proposed system is capable of providing secure communication from an eavesdropper with no decrease in performance as compared with the baseline case of a standard OFDM transceiver. The techniques developed in this paper provide greater security to OFDM-based wireless communication systems.

Appendix

Specific details regarding the coarse timing (Section A) and fine timing (Section A) implementation of the OFDM synchronizer described in Section 6.1 are provided.

1.1 A.1 Coarse Timing

The coarse timing component of the synchronizer utilizes the received signal samples to determine the coarse start time of the packet and the iterative calculation of the modified correlation given by (7). The outputs of the module are provided to the CFO estimation block. The real and imaginary components of (7) are given as

$$ \begin{array}{@{}rcl@{}} &&Re\{P[n+1]\} = Re\{P[n]\}+r^{I}[n+L]r^{I}[n+2L]-r^{I}[n]r^{I}[n+L] \\ &&- r^{Q}[n]r^{Q}[n+L]+r^{Q}[n+L]r^{Q}[n+2L],and \end{array} $$

(17)

$$ \begin{array}{@{}rcl@{}} &&Im\{P[n+1]\} = Im\{P[n]\}+r^{I}[n+L]r^{Q}[n+2L]\\ &&-r^{I}[n+2L]r^{Q}[n+L]-r^{I}[n]r^{Q}[n+L]+r^{I}[n+L]r^{Q}[n], \end{array} $$

(18)

respectively, where the superscript {⋅}^I denotes the in-phase component of the received signal and {⋅}^Q represents the quadrature phase. The real-valued calculation of the signal energy is derived as

$$ \begin{array}{@{}rcl@{}} R[n+1] &=& R[n]+|(r^{I}[n])^{2}+(r^{Q}[n])^{2}- \\ &&(r^{I}[n+2L])^{2}-(r^{Q}[n+2L])^{2}|^{2}. \end{array} $$

(19)

A filtered timing metric is calculated as

$$ M_{LPF}[n] = \frac{1}{C}\sum\limits_{k=0}^{C-1} \frac{|P^{I}[n-k]+P^{Q}[n-k]|^{2}}{|R[n-k]|^{2}}, $$

(20)

where the window is set to the cyclic prefix length C. The strength of P[n] varies and, therefore, requires normalization by R[n], with a result as given by M_LPF[n], which is used to set a hard threshold. The coarse timing point is selected at the maximum of the M_LPF[n] metric. The inputs to the implemented unmodified synchronizer are the real and imaginary signal samples each with data type S16_14 and a coarse timing comparison threshold of data type U16_0. The resulting threshold addresses a Block RAM, which allows for the setting of fractional values. The calculations of (17), (18), and (19) are performed in parallel to reduce latency, but require 12 multipliers to implement the complex operations. The timing metric given by (20) is calculated using a divider block after bit-shifting the auto-correlation values to meet input constraints, with the resulting output being of data type U16_14. Low pass filtering is implemented with parallel addressable shift registers, cascaded addition, and a constant multiplier. Relational operators are used for threshold crossing throughout the implementation of the synchronizer. The number of time samples above the timing metric threshold is calculated using a counter, with crossings determined by rise and fall edge detection. The output of the counter is used to address shift registers for proper signal alignment in time.

1.2 A.2 Fine Timing

Fine timing is completed using the output samples of the CFO correction block and a threshold value, with the output being the corrected samples and a corresponding alignment signal. Fine timing and determination of the correct CFO estimate are performed by calculating the cross-correlation given by

$$ F_{i}[n] = \underset{m}{\sum} \hat{x}_{i}[m+n] S^{*}[m], $$

(21)

where S[m] is the reference signal provided to the receiver. The separate real and imaginary components of the cross-correlation are given as

$$ Re\{F_{i}[n]\} = F_{i}^{II}[n]+F_{i}^{QQ}[n], \textrm{ and} $$

(22)

$$ Im\{F_{i}[n]\} = F_{i}^{QI}[n]-F_{i}^{IQ}[n], $$

(23)

respectively, where the superscript pair corresponds to the component of the corrected signal and the component of the reference signal used in individual cross-correlation calculations. The absolute value of the F_i signals are compared with a hard threshold to detect the start of the packet. Due to the structure of the preamble, there are ideally two events at which a crossing occurs, spaced by N samples. The first crossing corresponds to the start of the packet. The distance between multiple threshold events is used to filter incorrect estimates. The maximum values of F₁ and F₂ are compared to determine which CFO estimate is correct. The incorrectly adjusted signal results in a non-coherent correlation and yields low values.

The real and imaginary components of the CFO corrected signals each with data type S16_14 and the fine timing comparison threshold with data type U16_0 are provided as inputs to the implementation of the unmodified synchronizer on the FPGA. Multiplications are avoided by quantizing the signals to ± 1 and using conditional sign inversion with multiplexers. The reference signals are extracted using bit slices of data type U32_0 for decimal equivalent constants of the binary sequence. Cascaded addition is used to improve computational efficiency, and relational operators are used to compare the computed correlations with the hard threshold. The CFO corrected signals given by (10) are delayed to align with the calculated correlations to minimize loss in precision. The outputs of the unmodified synchronizer for packet alignment are the frequency corrected in-phase and quadrature phase samples with data type S16_14 and the corresponding timing pulses of data type U1_0 from the correlator.