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Low-power and high-performance adaptive routing in on-chip networks

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Abstract

Performance and power are two conflict requirements in a NoC. It is attractive to propose a low-power and high-performance routing scheme. A new low-power fully adaptive routing algorithm is proposed for virtual cut-through or wormhole switched networks-on-chip. The following new techniques are proposed: (1) multiple packets can be delivered across the same physical channel via different bypassing channels, (2) a low-power bypassing hop can include both x and y channels, (3) a new low-power routing selection function is defined for more power reduction, (4) a new limited-global control signaling scheme is proposed, (5) a new cycle-accurate system-level power estimation model is proposed, and (6) bypassing hops of any lengths and the normal hops in the original network can share the same virtual channels. Simulation results are presented to evaluate the performance and power by comparison with some previous methods.

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  1. The School of Software, Tsinghua University, Beijing, 100084, People’s Republic of China

    Dong Xiang & Qunyang Pan

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  1. Dong Xiang
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  2. Qunyang Pan
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Correspondence to Qunyang Pan.

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Xiang, D., Pan, Q. Low-power and high-performance adaptive routing in on-chip networks. CCF Trans. HPC 1, 92–110 (2019). https://doi.org/10.1007/s42514-019-00009-5

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