Abstract
Recently, many researches have proposed computing-in-memory architectures trying to solve von Neumann bottleneck issue. Most of the proposed architectures can only perform some application-specific logic functions. However, the scheme that supports general purpose computing is more meaningful for the complete realization of in-memory computing. A reconfigurable computing-in-memory architecture for general purpose computing based on STT-MRAM (GCIM) is proposed in this paper. The proposed GCIM could significantly reduce the energy consumption of data transformation and effectively process both fix-point calculation and float-point calculation in parallel. In our design, the STT-MRAM array is divided into four subarrays in order to achieve the reconfigurability. With a specified array connector, the four subarrays can work independently at the same time or work together as a whole array. The proposed architecture is evaluated using Cadence Virtuoso. The simulation results show that the proposed architecture consumes less energy when performing fix-point or float-point operations.
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Acknowledgements
This work was supported in part by the National Natural Science Foundation of China under Grant 61701013, in part by State Key Laboratory of Software Development Environment under Grant SKLSDE-2018ZX-07, in part by National Key Technology Program of China under Grant 2017ZX01032101, in part by State Key Laboratory of Computer Architecture under Grant CARCH201917 and in part by the 111 Talent Program under Grant B16001.
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Pan, Y., Jia, X., Cheng, Z. et al. An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing. CCF Trans. HPC 2, 272–281 (2020). https://doi.org/10.1007/s42514-020-00038-5
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DOI: https://doi.org/10.1007/s42514-020-00038-5