Abstract
By replacing multiplication with XNOR operation, Binarized Neural Networks (BNN) are hardware-friendly and extremely suitable for FPGA acceleration. Previous researches highlighted the potential exploitation of BNNs performance. However, most of the present researches targeted at minimizing chip areas. They achieved excellent energy and resource efficiency in small FPGA while the results in larger FPGA were unsatisfying. Thus, we proposed a scalable fully pipelined BNN architecture, which targeted on maximizing throughput and keeping energy and resource efficiency in large FPGA. By exploiting multi-levels parallelism and balancing pipeline stages, it achieved excellent performance. Moreover, we shared on-chip memory and balanced the computation resources to further utilizing the resource. Then a methodology is proposed that explores design space for the optimal configuration. This work is evaluated based on Xilinx UltraScale XCKU115. The results show that the proposed architecture achieves 2.24×–11.24× performance and 2.43×–11.79× resource efficiency improvement compared with other BNN accelerators.
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This work is supported by National Science and Technology Major Project 2018ZX01028101.
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This paper is submitted for possible publication in the Special Issue on Reliability and Power Efficiency for HPC.
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Han, Z., Jiang, J., Xu, J. et al. A high-throughput scalable BNN accelerator with fully pipelined architecture. CCF Trans. HPC 3, 17–30 (2021). https://doi.org/10.1007/s42514-020-00059-0
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DOI: https://doi.org/10.1007/s42514-020-00059-0