Abstract
With high performance computing (HPC) continues evolving, high performance microprocessor, which is the key building block of super computer, becomes the jewel in the crown of HPC. To this end, we propose MT-3000, a heterogeneous multi-zone processor for HPC, which is entirely designed and implemented by National University of Defense Technology. MT-3000 contains 16 general purpose CPUs, 96 control cores and 1536 accelerator cores, which are grouped into a general purpose zone and an acceleration zone. The acceleration zone is further divided into four clusters. Through sophisticated designs of such multi-zone organization, interconnection, and memory subsystem, MT-3000 achieves 11.6 TFLOPS double precision performance and 45.4 Gflops/w power efficiency when operating at 1.2 GHz. Based on the MT-3000 chip, a super computer prototype with nearly 12 peta flops peak performance is implemented, achieving 80% computation efficiency for Linpack. The possibility of a larger scale super computer construction based on MT-3000 chip is also elaborated in this paper.
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This work was supported by National Key Research and Development Program of China (No. 2018YFB0204301).
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Lu, K., Wang, Y., Guo, Y. et al. MT-3000: a heterogeneous multi-zone processor for HPC. CCF Trans. HPC 4, 150–164 (2022). https://doi.org/10.1007/s42514-022-00095-y
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DOI: https://doi.org/10.1007/s42514-022-00095-y