Abstract
Due to the bionic features, neuromorphic computing has achieved higher energy efficiency than deep learning in many fields in recent years. Similar to the biological brain, the memory of synapses and weights occupy a large area in a neuromorphic processor. The prior neuromorphic processors meet the challenge of the large area of the memory organization. In this work, based on the characteristics of the brain and spiking neural networks (SNNs), we propose a set-associative memory organization and a compressed SRAM memory organization with an adjacent matrix of synapses for loose and tight coupling structures in SNN respectively to construct an area-efficient memory organization for generalized neuromorphic architectures. A ping-pong memory is also proposed for the logic neuron number expansion. Experiments show that our methods use less chip area and consume less power than the CAM implementation in related work by 23.4–75.8% and 21.2–75.7% while bringing minor processor performance overhead.
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On behalf of all authors, the corresponding author states that there is no conflict of interest. This work is funded by National Key Research and Development Programs of China [Grant numbers 2018YFB2202603 and 2020AAA0104602].
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Yang, Z., Wang, L., Wang, Y. et al. Lotus: a memory organization for loose and tight coupling neurons in neuromorphic architecture. CCF Trans. HPC 4, 448–460 (2022). https://doi.org/10.1007/s42514-022-00113-z
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DOI: https://doi.org/10.1007/s42514-022-00113-z