Skip to main content

Advertisement

SpringerLink
Log in

Design of a Structured Hypercube Network Chip Topology Model for Energy Efficiency in Wireless Sensor Network Using Machine Learning

  • Original Research
  • Published:
SN Computer Science Aims and scope Submit manuscript

Abstract

Network on chips (NoCs) 3D design expansion is continuously changing to produce energy-efficient NoCs. In this production, the major requirement is to have continuous monitoring with great effort of engineering process and policies which tries to incorporate the machine learning techniques for producing EE-NoCs (energy-efficient NoCs). The learning is a method of neural network system. This thought process of machine learning art in producing EE-NoCs resulted in better production. The internal architecture framed is Power Gate Deployment, voltage instant changeovers, and scaling in the frequenting simultaneous reduction in power. Multiprocessor architecture and platform have been introduced to extend the applicability of Moore’s law. The solution for the multiprocessor system architecture is application-specific NoC architecture which are emerging as a leading technology. NoC can be useful in addressing many requirements such as inter-process communication, bandwidth, deadlock avoidance and routing structure. With power now the first order design constraint early stage estimation of NoC power, performance, and area has become important. The topology, switching and routing techniques are necessary in the NoC architecture design. This paper focuses on the n-dimension hypercube network on chip topological structure. It is used for more efficient performance and reliability for data communication. Therefore, in this paper, we are going to go through a bunch of different concepts, such as routing deadlock, and the router pipeline.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16

Similar content being viewed by others

References

  1. Kumar A, Kuchhal P, Singhal S. Network on chip for 3D Mesh structure with enhanced security algorithm in HDL environment. Int J Comput Appl (IJCA). 2012;59(17):6–13.

    Google Scholar 

  2. Pang K, Fresse V, Yao S, De Lima Jr OA. Task mapping and mesh topology exploration for an FPGA-based network on chip. Microprocessors Microsyst Elsevier. 2015;39:189–99.

    Article  Google Scholar 

  3. Tatas K, Siozios K, Soudris D, Jantsch A. Designing 2D and 3D network-on-chip architectures. Springer New York Heidelberg Dordrecht London. 2014. pp. 1–45.

  4. Wang F, Tang X, Xing Z. Applying partial power-gating to bit-sliced network-on-chip. Microelectron J Elsevier. 2015;46:1002–11.

    Article  Google Scholar 

  5. Chemli B, Zitouni A. A turn model based router design for 3D network on chip. World Appl Sci J. 2014;32(8):1499–505.

    Google Scholar 

  6. Elmiligi H, Gebali F, Watheq El-Kharashi M. Power-aware mapping for 3D-NoC designs using genetic algorithms. Proc Comput Sci Elsevier. 2014;34:538–43.

    Article  Google Scholar 

  7. Parmar SV, Kharche RB, Mamankar PV, Raza HM. Architecture and design of 4 x 4 x 4 NoC for multicore SoC. Int J Eng Adv Technol (IJEAT). 2015;4(4):2249–8958.

    Google Scholar 

  8. Chawade SD, Gaikwad MA, Patrikar RM. Review of XY routing algorithm for network-on-chip architecture. Int J Comput Appl. 2012;43(21):20–4.

    Google Scholar 

  9. Lee H-HS, Chakrabarty K. Test challenges for 3D integrated circuits. IEEE Des Test Comput. 2009;26:26–35.

    Article  Google Scholar 

  10. Jiang L, Xu Q, Eklow B. On effective TSV repair for 3D-stacked ICs, in DATE. 2012. pp. 793–8.

  11. Teuscher C. Nature-inspired interconnects for self-assembled large-scale network-on-chip designs. in Chaos: Interdisciplinary J Nonlinear Sci. 17, 2007.

  12. Petermann T, Rios PDL. Spatial small-world networks: a wiring-cost perspective, e-print arXiv:cond-mat/0501420, 2005.

  13. Das S, Lee D, Kim DH, Pande PP. Small-world network enabled energy efficient and robust 3D NoC architectures. In Proc. of GLSVLSI 2015.

  14. Boyan JA, Moore AW. Learning evaluation functions to improve optimization by local search. J Machine Learning Res. 2000;1:77–112.

    MATH  Google Scholar 

  15. Banerjee N, Vellanki P, Chatha KS. A power and performance model for network-on-chip architectures. in Proc. DATE, 2004. pp. 1250–55.

  16. Bona A, Zaccaria V, Zafalon R. System level power modelling and simulation of high-end industrial network-on-chip. in Proc. DATE, 2004. pp. 318–23.

  17. Briand LC, Freimut B, Vollei F. Using multiple adaptive regression splines to support decision making in code inspection. J Syst Software. 2004;73(2):205–17.

    Article  Google Scholar 

  18. Chan J, Parameswaran S. Node: energy macro-model extraction methodology for network on chip routers. in Proc. ICCAD, 2005. pp. 254–59.

  19. Dally WJ, Towles B. Route packets, not wires: on-chip interconnection networks. in Proc. DAC, 2001. pp. 684–89.

  20. Friedman JH. Multivariate adaptive regression splines. Ann Statist. 1991;19(1):1–66.

    MathSciNet  MATH  Google Scholar 

  21. Jeong K, Kahng AB, Samadi K. Architectural-level prediction of interconnect wire length and fanout. in Proc. ISOCC, 2009. pp. 53–56.

  22. Kahng AB, Li B, Peh L-S, Samadi K. ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration. in Proc. DATE, 2009. pp. 423–28.

  23. Kahng AB, Lin B, Samadi K. Improved on-chip router analytical power and area modeling. in Proc. ASPDAC, 2010. pp. 241–46.

  24. Kongetira P, Aingaran K, Olukotun K. Niagara: a 32-Way multithreaded SPARC processor. IEEE Micro. 2005;25(2):21–9.

    Article  Google Scholar 

  25. Ghosal P, Das TS. A novel routing algorithm for on-chip communication in NoC on diametrical 2D mesh interconnection architecture. Adv Comput Inf Technol, AISC 178, Springer-Verlag Berlin Heidelberg 2013, pp. 667–76.

  26. Jaiswal A, Kumar R. Review on machine learning algorithm in cancer prognosis and prediction. Int J All Res Edu Sci Methods, 2020;8(06). (Impact Factor: 4.597 ISSN (online):2455–6211).

  27. Mian SM, Kumar R. Time critical applications protocols and design issues in underwater wireless sensor networks. J Xidian Univ. 2020;14(04):414–6 (Impact Factor: 5.4 ISSN (online):1001-2400).

    Google Scholar 

  28. Jaiswal A, Kumar R. Review of machine learning algorithm on cancer classification for cancer prediction and detection. Int J Anal Exp Modal Anal (IJAEMA). 2019;11(12):1456–66 (Impact Factor: 6.3 ISSN (online): 0886-9367).

    Google Scholar 

  29. Kumar A, Tewaari N, Kumar R. Study towards the analytic approach for human computer interaction using machine learning. Int J Anal Exp Modal Anal (IJAEMA). 2019;11(12):1456–66 (Impact Factor: 6.3 ISSN (online): 0886-9367).

    Google Scholar 

  30. Mian SM, Kumar R. Security analysis and issues in underwater wireless sensor auditory and multipath network. Int J Anal Exp Modal Anal (IJAEMA). 2019;11(10):2269–71 (Impact Factor: 6.3 ISSN (online): 0886-9367).

    Google Scholar 

  31. Siddiqui MHF, Kumar R. Interpreting the Nature of Rainfall with AI and Big Data Models. 2020 International Conference on Intelligent Engineering and Management (ICIEM), London, 2020. pp. 306–10. https://doi.org/10.1109/ICIEM48762.2020.9160322.

  32. Pramod HB, Kumar R. Integration of dynamic security for lifetime enhancement in underwater sensor networks (February 23, 2019). Available at SSRN: https://ssrn.com/abstract=3340315 or https://doi.org/10.2139/ssrn.3340315.

  33. Singh SK, Jeong YS, Park JH. A deep learning-based IoT-oriented infrastructure for secure smart City. Sustain Cities Soc. 2020. https://doi.org/10.1016/j.scs.2020.102252 (IF: 5.280).

    Article  Google Scholar 

  34. Singh SK, Salim MM, Cha J, Pan Y, Park JH. Machine learning-based network sub-slicing framework in a sustainable 5G environment. Sustainability. 2020;12:6250. https://doi.org/10.3390/su12156250 (IF:2.576).

    Article  Google Scholar 

  35. Ogbebor JO, Imoize AL, Aaron-Anthony AA. Energy efficient design techniques in next-generation wireless communication networks: emerging trends and future directions, 2020. https://doi.org/10.1155/2020/7235362.

  36. Samara G, Ghadeer A, Mohammad A, Mohammad AK, Energy-efficiency routing algorithms in wireless sensor networks: a survey. Int J Sci Technol Res. 2020;9(1).

Download references

Funding

This research received no external funding.

Author information

Authors and Affiliations

  1. Uttarakhand Technical University, Dehradun, India

    Namit Gupta

  2. B T Kumaon Institute of Technology, Dwarahat, India

    Kunwar Singh Vaisla

  3. Teerthanker Mahaveer University, Moradabad, India

    Rajeev Kumar

Authors
  1. Namit Gupta
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Kunwar Singh Vaisla
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Rajeev Kumar
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

Conceptualization: NG; writing of the original draft preparation, writing of review and editing: NG, KSV and RK.

Corresponding author

Correspondence to Namit Gupta.

Ethics declarations

Conflict of Interest

The authors declare no conflict of interest.

Informed consent

None.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

This article is part of the topical collection “Computational Statistics” guest edited by Anish Gupta, Mike Hinchey, Vincenzo Puri, Zeev Zalevsky and Wan Abdul Rahim.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Gupta, N., Vaisla, K.S. & Kumar, R. Design of a Structured Hypercube Network Chip Topology Model for Energy Efficiency in Wireless Sensor Network Using Machine Learning. SN COMPUT. SCI. 2, 376 (2021). https://doi.org/10.1007/s42979-021-00766-7

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s42979-021-00766-7

Keywords

Search

Navigation