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Development of Noise Tolerant Document Image Binarization Technique Employing an Accurate Square Root Circuit

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Abstract

Stochastic computing (SC) is a re-emerging paradigm that is inherently immune towards noise and shows low area and power implementation of conventional binary logic based approaches. A stochastic square root circuit is proposed, which shows faster convergence and less hardware area compared to the state-of-the-art methods and can be used for efficient real time implementation of various algorithms that employ the square root circuit. In this paper, the Nick’s binarization algorithm is introduced as a case study to identify its promise using various statistical metrics. This paper also introduces structural modifications of some of the basic stochastic circuits obeying certain boundary conditions. A squarer circuit requiring the least number of delay elements is calculated to reduce the hardware cost.

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Authors and Affiliations

  1. Instrumentation and Electronics Engineering, Jadavpur University, Kolkata, West Bengal, India

    Shyamali Mitra & Debojyoti Banerjee

  2. Electronics and Telecommunication Engineering, Jadavpur University, Kolkata, West Bengal, India

    Mrinal K. Naskar

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  1. Shyamali Mitra
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  3. Mrinal K. Naskar
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This article is part of the topical collection “Advances in Applied Image Processing and Pattern Recognition” guest edited by K. C. Santosh.

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Mitra, S., Banerjee, D. & Naskar, M.K. Development of Noise Tolerant Document Image Binarization Technique Employing an Accurate Square Root Circuit. SN COMPUT. SCI. 4, 99 (2023). https://doi.org/10.1007/s42979-022-01470-w

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