Performance Analysis of FinFET-Based LVDS I/O Receiver Architecture

Abstract

This paper explains, the novel design architecture of a 3.2 Gbps PMOS-based low-voltage differential signaling (LVDS) receiver architecture using 18 nm FinFET technology. The designed LVDS receiver meets the requirements of the high data rates applications. The pre-amplifier stage and the differential to the single-ended stage with buffer make up the fundamental building blocks of this LVDS receiver architecture. LVDS signal is amplified by a pre-amplifier and after pre-amplifying, the signal is converted from double ended to single ended through a differential amplifier, the resulting differential outputs generate a CMOS signal. The study suggests a LVDS receiver with a current source bias circuit developed in the 18 nm standard FinFET process for the DAC of the DDS system. The outcomes of the design simulation demonstrate that the suggested LVDS receiver is appropriate for the IEEE LVDS standard. This architecture achieved a data rate of 3.2 Gbps with 1.6 GHz frequency, the circuit consumes 6.805 mW of power, 3.780 mA of current, and AC simulation gain is about 13.3 dB from a 1.8 V supply at a typical corner level. The proposed LVDS receiver circuit resulting a transient simulation of rising and falling delays, also with the help of eye diagram simulation, the rise and fall jitter is calculated for typical, slow, and fast corners with a low- and high-temperature range. The proposed LVDS receiver architecture was implemented using the Cadence Virtuoso tool with an 18 nm FinFET technology node.