1 Introduction

The inexpensive layout design of multipliers of the AND gate is used to perform both the partial product and the multiplication of multipliers. The multiplier's internal structure is determined by the relative sizes of the multiplicand and the multiplier. The multiplier is built using a dynamic decomposition method in which the multiplier and multiplicand sizes are predetermined. To perform the multiplication operation, a series of additions must be applied [1]. The equation illustrating the multiplication's internal additive process is: (1). [2,3,4] increases system speed while decreasing energy consumption. To accomplish high-speed processing, multipliers are used as appropriate components. Utilizing multipliers efficiently can boost the speed of mathematical operations and algorithms. Addition and shifting are the workhorses of digital processing. A system that uses parallel multipliers to improve the speed of multiplication and shift operations is presented. The design and implementation of multipliers can be performed using a wide variety of architectures and algorithms. The goals of these architectures and algorithms are simplification in terms of complexity, number of parts, power consumption, and runtime [5, 6]. One such efficient multiplier that lessens the total number of integrated additions is the Baugh-Wooley [7, 8] multiplier. This multiplier's operational behavior can be thought of as occurring in a series of stages. The functional responsibilities of each stage are linked to the subsequent stage and the previous stage to decrease the power consumption and execution time, respectively. This study integrates quaternary logic and the Walsh Tree algorithm to boost the efficiency of the Baugh-Wooley multiplier.

The AND gate is used to perform both the partial product and the multiplication in multipliers. The multiplier's internal structure is determined by the relative sizes of the multiplicand and the multiplier. The multiplier is built using a dynamic decomposition method in which the multiplier and multiplicand sizes are predetermined. To perform the multiplication operation, a series of additions must be applied [1, 9]. The equation illustrating the multiplication's internal additive process is: (1).

$$\left. {\begin{array}{*{20}c} {P\left( {m + n} \right) = A\left( m \right)B\left( n \right)} \\ { = { }\mathop \sum \limits_{i = 0}^{m - 1} \mathop \sum \limits_{j = 0}^{n - 1} A\left( i \right)B\left( j \right)2^{i + j} } \\ \end{array} } \right\}$$
(1)

The inputs A and B are binary sequences of lengths m and n, respectively.

The steps of the algorithm for multiplication are listed below. An algorithm was used to add the digits. Partial products are calculated using a sequential serial adder. Parallel multiplication is achieved by adding these partial products together [10, 11].

  • Check the least significant bit of the multiplier; if it is ‘1’, then add the multiplier into an accumulator.

  • Apply a one-bit shift to the right as well as a one-bit shift to the left.

  • This process is repeated for all bits until the multiplier is not set to 0.

In regard to efficiency, power consumption, and overall complexity, serial multipliers [12, 13] shine. This multiplier calculates m*n partial products with a single adder. A schematic of the serial multiplier is shown in Fig. 1. This circuit makes use of a time-locked stream of data. Each clock pulse triggers a shift operation on the incoming bitwise input. The multiplicand and multiplier bits are retrieved at regular intervals. The extracted bits are then fed into a partial product adder. The data processing clock is independent of the reset clock in this design [14,15,16]. The complexity of the architecture is given by O (m, n).

Fig. 1
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Serial multiplier

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The serial/parallel multiplier, depicted in Fig. 2, is another popular and useful multiplier. Bits that are input in parallel are converted into sequential bits and zeros by this multiplier. Every time the lock is activated, N partial products are calculated. The cycle after that adds up the numbers in one column of the multiplication table. The product of the multiplication is written to the output register. The final result requires N + M clock cycles [17, 18].

Fig. 2
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Serial/parallel multiplier

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To perform parallel multiplication, a simple array multiplier can be used. Figure 3 shows the circuit diagram of the 4 × 4 array multiplier. Array multiplies imply stagewise processing through parallel adders. The partial input is taken from an array of bits. Rowwise array processing is carried out in this multiplier. In each stage, the multiplier performs the partial products using Full Adders. This process can be performed partially so that full adder-based work can be performed. This work can be performed for n bits by using an n-bit array specification that can be processed vertically and horizontally [19,20,21]. A 16-bit multiplier can be specified such that the bit delay can be obtained during the processing of the full adder. The pipelining of the array system is analyzed to perform parallel multiplication as well as simultaneous work. The pipelining can be increased to optimize the multiplier output. The number of pipelining layers increases the latency and the area of the multiplier. A pipelined-based array is defined to avoid array-level analysis and the clock of the processor [22,23,24,25]. The intermediate analysis, along with the partial sum, is defined to obtain the repeated propagation over the system. This process is repeated under the specifications of the array multiplier, and the depth of the array is specified over the system. This kind of work is defined under the specification of a partial product [26, 27].

Fig. 3
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4 × 4 array multiplier

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1.1 Problem Definition

In digital signal processing, multipliers are highly important for solving different arithmetic and logical problems. One of the primary requirements of digital signal processing is multiplication. This multiplication process can be performed by using different multiplication algorithms. A multiplier is a combinational circuit that can be used to perform multiplication. Conventional multipliers are designed with complex structures and high-power requirements. The performance of the multiplier directly affects the performance of the system. With technological advancements, the size of transistors is decreasing, which reduces the component area and power requirements. Various serial, parallel, shift, and array multipliers were also designed to improve the performance of the system. Various architectural designs, component integrations, and algorithms were adopted within multiplier designs to improve the computational speed and reduce power consumption. In the present work, the optimization of the Baugh-Wooley architecture is presented. In this new design, a quaternary logic-based look-ahead carry multiplier is used. The Wallace tree algorithm is also integrated for the effective integration of components and for carrying out effective operations. The main objective of the designed system is to reduce power consumption and delay and improve the performance of the existing Baugh Wooley Multiplier.

In this paper, an improved Baugh Wooley multiplier is designed to reduce the power consumption and latency time. The designed multiplier is integrated with a quaternary adaptive carry look-ahead adder. The Wallace tree algorithm is integrated into this multiplier to effectively enhance the performance. In this section, different types of multipliers are discussed. The complexities and features of the multipliers are described in this section. In Sect. 2, the work and improvements investigated by earlier research on the Baugh Wooley design, the Wallace tree algorithm, and quaternary logic are discussed. In Sect. 3, the architecture design of the proposed Baugh Wooley multiplier is provided. The algorithmic and functional description of this improved multiplier is also provided in this section. In Sect. 4, simulation and analysis results are provided for the conventional Baugh Wooley multiplier. In Sect. 5, the conclusion of this research is provided.

2 Related Work

In describing microcontrollers and microprocessors, architectural improvements are necessary for optimizing the performance and reducing the size of the component or system. Various kinds of serial and parallel multipliers have been designed by researchers for optimizing specific functionalities or operations, such as shifts, multiplication, and partial products. Baugh Wooley is a multiplier that is optimized by researchers by integrating various additional components and algorithms. In this section, the research contributions of earlier researchers are described.

Bhoi et al. [2] integrated quantum dot cellular automata (QCA) technology within the Baugh-Weoley multiplier to optimize computational performance. In this architecture, a single layer-based wire-crossing mechanism is used for minimizing clock phasing. The designed layout was scalable and achieved effective preliminary results. Raveendran et al. [28] presented a novel inexact Baugh Wooley Wallace tree multiplier by optimizing the compressor of an existing architecture. Reversible logic was applied in this work with 4:2 compression and a 12.5% error rate. The realization metrics were analyzed for this multiplier, and its scope for complex applications was identified. The structural similarity measure-based method was defined and achieved a high accuracy rate of more than 97.1%. Xiong et al. [3] designed the Wallace tree architecture based on 8-bit Baugh Wooley 2's complement multiplier. The Wallace tree architecture is integrated specifically for quicker partial products. The architecture is also integrated with carry-save adders to reduce the number of additional cycles. The array architecture was adopted in this design to reduce power consumption. Gudivada et al. [4] employed quantum-dot cellular automata-based nanotechnology to design a 1-bit full adder. This lower-power-consumption-based design is integrated within the Baugh-Wooley multiplier. This improved design ensured a reduction in cell count and energy consumption and achieved efficient blocking. Biradar et al. [5] designed an improved Baugh-Wooley and Braun multiplier for unsigned and signed number multiplication. To reduce the size and power consumption, the adder is designed using CMOS, domino, and split path data-driven dynamic logic (SPD3L). The implementation results confirmed that the designed multiplier reduced energy consumption and achieved a significant performance gain. Asati et al. [6] designed a novel pipelined 8 × 8 signed Baugh Wooley multiplier and implemented it using CMOS TSPC logic at 0.6 µm. The designed model effectively reduced the transistor, power consumption, and delay. Muley et al. [7] designed a novel Baugh Wooley and Wallace tree multiplier and implemented it using a 2-phase clocked adiabatic static CMOS logic (2PASCL). The designed architecture has an energy consumption of up to 62.66% in comparison with that of the static CMOS logic-based Wallace tree multiplier. Pudi et al. [29] employed QCA design technology to optimize the performance of the Baugh-Wooley Multiplier. The multiplier was designed for the multiplication of a pair of 2's complement numbers. The simulation results revealed that the proposed design reduced the area and delay and improved the throughput. Sjalander et al. [1] used the Baugh Wooley algorithm with an HPM reduction tree for designing a high-speed and low-power multiplier. The adoption of nanotechnologies reduced the size, delay, and power consumption in the design of the modified multiplier. Tu et al. [10] applied the skin-tolerant domino technique to design an improved Baugh Wooley multiplier. In this improved design, four overlapping clock signals were used for the AND gate, NAND gate, half adder, and full adder. The carry save vector was employed for merging. The simulation results confirm the significant improvement achieved in performance. Warrier et al. [12] proposed a pipelined MAC architecture and integrated it within a 16 × 16 multiplier. The integration is performed using the Baugh-Wooley algorithm with reduced energy consumption and effective clock gating. The designed architecture reduced the power consumption by 30 to 80% compared with that of existing contemporary MAC architectures. Tu et al. [13] designed a pipelined reconfiguration and fixed width-based Baugh Wooley multiplier design framework. This framework provided four configuration modes. This pipelined reconfiguration-based design effectively reduced the power consumption.

Mukherjee et al. [18] defined a generic model for the Baugh Wooley Multiplier. A linear carry-select adder was used instead of the conventional Baugh Wooley multiplier. The author defined a postsynthesis analysis to attain the results. Mohanty et al. [17] defined an efficient Baugh Wooley architecture to perform signed and unsigned multiplication. The work was defined for parallel multipliers with useless adders or less. An iterative process was defined to perform the multiplication in a series of add operations. This approach simplified the system complexity and increased the computational effort. Another work on low-power array specification architecture was defined by Bajaj et al. [30] on an unsigned system with signed multiplication. The author defined the work for the Baugh Wooley multiplier. The reduced power consumption is based on the optimum approach within the multiplier. Another study on the signed array multiplier was performed by Das et al. [31]. The author defined a novel architecture for a binary signed multiplier using the Baugh Wooley algorithm. The work was defined for a 2 × 2 multiplier, and the negative operand was adjusted to improve the system performance and reduce the computations.

Di et al. [32] reconfigured the multiplier design to reduce the power consumption of the system. The author defined a two-complemented-based signed multiplier scheme. The author divided the input data into smaller blocks and reduced the computations. The sign-bit processing-based method avoided negative operands and reduced the delay and power consumption. Bansal et al. [33] defined a 64 × 64 bit multiplier using a radix 2 modified booth algorithm. The author improved the multiplier performance by including a modified Wallace structure. The author defined the fixed-length structure and presented the work with an array of coprocessor systems. The proposed pipelined system reduced the computational latency and delay. Another study on a modified booth encoder and multiplier system was performed by Rajput et al. [34]. The author defined the design and multiplication phase under the multiplication operation in signed number analysis. The authors used the saved adder tree and final carry look-ahead adder to speed up the multiplier operation. The designed component reduced energy consumption. Another study on high-speed multipliers was performed by Saokar [35]. The author defined the system with a floating point multiplier. The author proposed a method for fixed-point multiplication based on Vedic mathematics.

Vakili et al. [36] introduced an effective and robust approximation method to multiply the signed number on FPGAs. This approach integrated a segmentation method within the Baugh-Wooley multiplication algorithm to optimize the outcome. Each segment was processed within a look-up table to generate accurate and quick results. The model achieved 53.6% utilization of resources in comparison with the INT8 Xilinx multiplier. Kishore et al. [37] used a Quantum-dot Cellular Automata (QCA) mechanism within CMOS technology to optimize the multiplication process. The model was defined to enhance the performance of nanodevices. The author used the parallel array multiplier with Braun multiplier and ripple carry adder to reduce power consumption. This QCA-enhanced Baugh Wooly multiplier was comparatively small, requires lesser power, and provides high performance in nanodevices. The computational capabilities of this model was efficient. Pakkiraiah et al. [38] provided an extension over the existing Baugh-Wooley multiplier design by reducing the number of gate counts and optimizing the power consumption and speed. The reversible logic gates were used to reduce the power consumption and to improve the computational efficiency. The method achieved effective results against white cells, pink cells and reversible full adder. Raj et al. [39] proposed Multiple Control Toffoli and Multiple Control Fredrick and Reversible logic gate-based Baugh Wooley multiplier design to reduce the hardware complexity and to optimize the performance. The designed architecture has taken lesser area with low power consumption. The processing speed was also improved in this architecture with lesser power usage. The analysis results observed a 23.77% and 16.88% reduction in processing delay against FPGA-BWM-RL-TG and FPGA-BWM-TG-FG architectures.

Kishore et al. [40] used the modified gate diffusion input technique to optimize the power consumption of the Baugh Wooley Multiplier. The model was implemented using GDI, CMOS, and MGDI methods. This model observed that the CMOS-based Baugh Wooley multiplier used more transistors and consumed higher power with maximum delay. The multiplier with 32 nm technology provided the most effective results. Beura et al. [41] integrated a compressor within the Baugh-Wooley multiplier to obtain the addition of partial products. The algorithm was defined with the inclusion of 4:2 compressor in the product bit array. The model was designed to reduce total error distance by balancing the overestimation of design time. The minimum single-to-noise ratio was achieved in this model when implemented for edge detection. The proposed design improved the error tolerance and reduced the area-delay tradeoff. This model achieved better accuracy and improved the reliability of the system. Thamizharasan et al. [42] provided a hybrid compressor-based multiplier that was implemented with Field Programmable Gate Array. It was a modification over the Vedic multiplier to optimize the performance of signal/image processing applications. The results identified that the model improved the processing speed upto 35.83% against the Array multiplier, 24.49% against the Carry Look ahead adder-based Vedic multiplier, 20.65% against Ripple carray adder Ripple-based Vedic multiplier, 21.65% against the Booth multiplier and 7.15% hybrid vedic multiplier.

3 Research Methodology

Multiplication is the core operation generally used in most arithmetic and logical applications. A multiplier is a combinational circuit that is used for various arithmetic and logical operations, including multiplication. Multiplication is a complex problem that has high computational and power requirements. Various serial, parallel, and array multipliers were investigated and optimized by researchers by integrating various algorithmic methods and components. Baugh Wooley is a multiplier that uses sign bits effectively via a multiplication algorithm. This technique accepts the 2's complement number and provides an effective way to multiply over regular multipliers. The present work involves optimizing the functional behavior and structure of Baugh Wooley multipliers. The structural improvement presented in this work is the use of a Quaternary logic adaptive look ahead carry adder. Functional improvement is achieved by integrating the algorithmic flow with the Wallace Tree algorithm. The objective of this improved and optimized Baugh Wooley multiplier is to reduce the power consumption and execution time and to enhance the performance of the system (Fig. 4).

Fig. 4
figure 4

Full functional architecture of the proposed quadetary logic and Wallace tree algorithm-based Baugh-Wooley multiplier

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3.1 Baugh Wooley Multiplier

In this research, multiplication optimization is suggested using the improved Baugh-Wooley algorithm. Baugh Wooley accepts signed digital data as input and executes array multiplication. The 2's complement is used to represent the negative number. The algorithm accepts the 8-bit format and applies partial multiplication. N-bit array-based partial production creation and processing via Wooley array multiplication are described in this subsection. Let A and B be N-bit array representations of two signed numbers. Equation (2) provides the representation of the number in signed bit format.

$$\left. {\begin{array}{*{20}c} {A = \left( {a_{N - 1} \ldots a_{0} } \right) = - a_{N - 1} \cdot 2^{N - 1} + \mathop \sum \limits_{i = 0}^{N - 2} a_{i} \cdot 2^{i} } \\ {B = \left( {b_{N - 1} \ldots b_{0} } \right) = - b_{N - 1} \cdot 2^{N - 1} + \mathop \sum \limits_{i = 0}^{N - 2} b_{i} \cdot 2^{i} } \\ \end{array} } \right\}$$
(2)

The multiplication of A and B is provided in Eq. (3):

$${\text{A}} \cdot {\text{B}} = a_{N - 1} .b_{N - 1} 2^{2N - 2} + \mathop \sum \limits_{i = 0}^{N - 2} \mathop \sum \limits_{j = 0}^{N - 2} a_{i} b_{i} 2^{i + j} - a_{N - 1} \mathop \sum \limits_{i = 0}^{N - 2} b_{i} 2^{N + i - 1} - b_{N - 1} \mathop \sum \limits_{i = 0}^{N - 2} a_{i} 2^{N + i - 1}$$
(3)

Equation (2) shows that multiplication is performed by using the adder and subtractor cells. Equation (4) reframes the negative cell equation using only adder cells.

$$- a_{N - 1} \mathop \sum \limits_{i = 0}^{N - 2} b_{i} 2^{N + i - 1} = a_{N - 1} \cdot \left( { - 2^{2N - 2} + 2^{N - 1} + \mathop \sum \limits_{i = 0}^{N - 2} b_{i} 2^{i + N - 1} } \right)$$
(4)

Now, by using these adder cells, Eq. (3) is reframed to Eq. (5). In Eq. (5), Eq. (4) is substituted.

$${\text{A}} \cdot {\text{B}} = a_{N - 1} \cdot b_{N - 1} 2^{2N - 2} + \mathop \sum \limits_{i = 0}^{N - 2} \mathop \sum \limits_{j = 0}^{N - 2} a_{i} b_{i} 2^{i + j} + a_{N - 1} \cdot \left( { - 2^{2N - 2} + 2^{N - 1} + \mathop \sum \limits_{i = 0}^{N - 2} b_{i} 2^{i + N - 1} } \right) + b_{N - 1} \cdot \left( { - 2^{2N - 2} + 2^{N - 1} + \mathop \sum \limits_{i = 0}^{N - 2} a_{i} 2^{i + N - 1} } \right)$$
(5)

The functional flow of the Baugh Wooley array multiplier is provided below:

  • The most significant bits of the first N − 1 partial product row and all bits other than MSB of the last partial product row are inverted

  • Replace the Nth bit with '1'

  • Invert the MSB of the Final Results.

These steps show that the partial product of array bits is generated by applying the AND gate to operand bits. The obtained partial product is inverted, and the NAND gate is used for this inversion. Now, the nth bit is replaced by '1'. A block diagram of the 4 × 4 Baugh Wooley multiplier is shown in Fig. 5. In this figure, two kinds of cells are used: gray cells and white cells. To design the circuit diagram of the Baugh Wooley multiplier, the following steps are carried out. A broader view of this design process is provided in Fig. 4.

  • Design a 1-bit Quaternary logic-based look carry ahead Full Adder (FA)

  • Design of Gray and White Cells using the Designed FA

  • Employ the Wallace Tree Algorithm.

Fig. 5
figure 5

Block diagram of the Baugh Wooley multiplier

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3.2 Wallace Tree Algorithm

WALLACE provides an effective parallel multiplier algorithm and phenomenon with fewer gates. It is one of the faster multipliers available with multiple schemes. In this work, a quaternary component integrated Wallace tree algorithm is integrated within the Baugh Wooley Multiplier to optimize its functionality. This algorithm adapts to reduce the number of adder stages. The quaternary logic-based look ahead carry adder generates the summation of partial products. The half and full adders using quaternary logic are integrated to reduce the number of rows and bits at different stages of this Wallace Tree. This tree-based Wallace algorithm is less complex than other algorithms and uses serial multiplication. The algorithmic steps of the proposed Wallace tree-based multiplication with quaternary logic components are described below. The architecture of this Wallace tree functionality is provided in Fig. 6.

  1. 1.

    Take the quaternary bits as an argument and perform multiplication to generate N-bit results. The look carry ahead adder is used with a weighted value to perform the positional multiplication.

  2. 2.

    The partial product-driven layer multiplication reduces the number of required components.

  3. 3.

    Use look carry ahead adder to add number.

  4. 4.

    Partial products are generated at each stage by integrating layered quaternary logic-based adders, and carry is forwarded sequentially at the same stage to process the next two data values.

  5. 5.

    This method is applied in hierarchical order and processed in two layers by using quaternary look carry ahead adders.

  6. 6.

    In the final stage, the quaternary look-ahead carry adder is applied to generate the final products p1 to p8, as shown in Fig. 6.

Fig. 6
figure 6

Functional architecture of the Wallace tree algorithm

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The effectiveness of this Wallace Tree algorithm within the Baugh Wooley multiplier is to reduce the layers by improving the structure and components of the standard architecture. This improved structure reduces the number of layers. The layered-driven partial products are computed, and the final addition is performed at the last layer. The proposed architecture reduced the number of components and computations, which reduced the energy consumption and improved the performance of the multiplier in comparison with the existing multiplier architecture.

3.3 Quaternary Logic-Based Look Carry Ahead Adder

In this paper, a Quaternary logic and Wallace Tree-integrated Baugh Wooley multiplier architecture is proposed to reduce power consumption and improve architectural behavior. The main component used in this model is quaternary logic adaptive Carry Look Ahead Adder. It is a lightweight sequential processor that performs a series of adder operations. The look-ahead carry adder reduces the computation time by adding two quaternary numbers. It uses two signals called propagation and generation. The bit position-based carry propagation is performed at the LSB position. A block diagram of the quaternary logic bit-based full adder is provided in Fig. 7. It is composed of two half-adders. In this adder, the inputs use the generate and propagate structure and pass the carry sequentially. The first two bits are passed to the first half of the adder as input, and the result is taken as the sum and carry. This sum and the third quaternary digits are passed to the second half of the adder, and the sum and carry are generated as the final output.

Fig. 7
figure 7

Block diagram of quaternary full adder

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In this research, the quaternary logic-based look ahead carry adder is used in different layers of the Wallace tree and Baugh-Wooly architecture. The circuit diagram of the look ahead carry adder is provided in Fig. 8. It can be used to perform large multiplication operations in terms of a group of bits. Here, g0, g1, g2, and g3 are the groups of bits. The unit generator is applied to these groups to obtain the predicted information called p0, p1, p2, and p3. The predicted information is collected for each block, and the carry is generated for processing them sequentially. As the block-based information is processed, the method provides higher performance with less power consumption. This standard architecture is improved in this work by specifying the groups in the form of quaternary logic bits. Figure 9 shows the block diagram of a 4-bit adder applied to the Quaternary logic number.

Fig. 8
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Circuit diagram of the look-ahead carry adder

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Fig. 9
figure 9

Functional architecture 4-bit quaternary look ahead carry adder

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Figure 9 shows the functional architecture of a 4-bit adder that is composed of four quaternary logic-based look-ahead carry adders. The first two quaternary bits are passed as inputs to the first adder, and the sum and carry are taken as inputs. The sum is taken as the output, and the carry is passed to the next adder as the second input. The third input of 4 bits is also passed to the second adder. Based on these three inputs, the sum and carry are generated. This process is repeated until all four bits are not passed, and the functional output of the 4th adder is not obtained.

Figure 10 shows the functional block diagram of the quaternary carrier look-ahead adder. The inputs are processed initially with a specification of generation and propagation functions. This stage performs the bit grouping and transition of quaternary data to the adaptive bit form. Once this transformation is complete, the carry looks ahead adder is applied. The generated P and G are processed, and every bit position is specified. After processing the adder, the carry is obtained and processed in the final stage, where the addition is performed. Equation (6) shows the functional process of this quaternary carry look-ahead adder.

$$C_{i} = g_{i - 1} + \mathop \sum \limits_{j = 0}^{i - 2} g_{j} \mathop \prod \limits_{k = j + 1}^{i - 1} p_{k} + C_{0} \mathop \prod \limits_{k = 0}^{i - 1} p_{k}$$
(6)
Fig. 10
figure 10

Block diagram of quaternary carry look-ahead adder

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4 Results and Discussion

In this paper, a quaternary logic and Wallace tree improved Baugh Wooley multiplier is designed. The designed model used functional complexity and lightweight components to reduce energy consumption and improve the performance of the multiplier. The proposed improved multiplier is designed and simulated in the active high-density lipoprotein (HDL) environment. This multiplier is designed for 180 nm technology. This architecture is simulated with a 1.8w power supply. The performance of the proposed improved multiplier is analyzed against existing serial and parallel multipliers. A comparative evaluation is performed using latency and power consumption parameters. The simulation results of the proposed protocol are provided in Figs. 11 and 12.

Fig. 11
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Simulation results for the quaternary look ahead carry adder

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Fig. 12
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Simulation results of the proposed improved multiplier

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The performance of the proposed improved multiplier is evaluated in terms of latency and power dissemination parameters. The energy dissemination is computed for the proposed layout using coherence vector simulation. The decreased energy dissemination confirms the reliability and effectiveness of the proposed architecture. The proposed architecture uses the partial product and level-based methods to reduce the complexity of the model. Performance was enhanced and functional processing delay is decreased with the addition of a quaternary look ahead carry adder as provided in the results of Figs. 13 and 14. The proposed architecture is compared against the CLA (Carry Look Ahead) Multiplier [43], QSDCLA (Quaternary Signed Digit-based Carry Look Ahead) Multiplier [43], Baugh Wooley Multiplier [44], Wallace Tree Multiplier [45], Quantum Digits and Component-based Wallace Tree Multiplier proposed by Hasan et al. and named this the Hasan Multiplier [46] and a fast adder improved Radix Adder [47].

Fig. 13
figure 13

Comparative performance analysis of the proposed improved multiplier against existing multipliers (power dissemination measure)

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Fig. 14
figure 14

Comparative performance analysis of the proposed improved multiplier against existing multipliers (latency measure)

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Figure 13 provides the power dissemination-based comparative analysis to validate the performance of the proposed quaternary logic improved and Wallace tree algorithm-integrated Baugh Wooley multiplier against the existing multipliers. The Carry Look Ahead (CLA) multiplier uses smaller sequential and pipelined components that increase power dissemination. The total power consumption of this architecture for the given input is 9.192 µW. The QSD-CLA (Quaternary Signed Digit Number System-based Carry Look Ahead) multiplier improved the architecture by processing on quaternary signed digits. The architecture became simpler, which reduced the power consumption, and the power consumption decreased to 7.89 µW. The Baugh–Woolley multiplier is a well-known multiplier that ensures high-speed architecture design and decomposition. This simplified and effective multiplier reduced the power dissemination to 4.3 µW. The wallace tree multiplier uses the compressor adder and carry select adder as the integrated components. These are light processing components that reduce power consumption and achieve a power dissemination of 4.11 µW. The Hasan multiplier is an improved Wallace tree multiplier constructed by using quantum cell-based processing. This quantum processing-based method increased the architectural complexity and level-specific computations. The power consumption is increased, and a 9.96 µW power dissemination rate is achieved. The radix-4 multiplier was improved by integrating a fast adder as the functional component. The integration of this component increased the architectural complexity, which achieved high performance but was compromised by power dissemination. The power recorded for this architecture is 1.693 µW. In this proposed multiplier architecture, partial product and multilayered processing were performed to reduce power dissemination. The proposed compact and improved architecture achieved 1.693 µw of power dissemination. The results confirm that the proposed architecture improved the reliability and reduced the cost of multiplier functioning.

Figure 14 provides the latency-based comparative analysis to validate the performance of the proposed improved architecture against the existing multipliers. The bar graph shows that the CLA (carry look ahead) multiplier is the least effective, with a maximum latency of 0.03469 ns. It is a sequential and pipelined multiplier and takes extra time because the number of variables is increased. The QSD-CLA (Quaternary Signed Digit Number System-based Carry Look Ahead) multiplier improved the performance with a simpler circuit. It reduced the latency to 0.01636 ns. The simpler and lighter-weight Baugh-Weololey device improved the performance and effectively reduced the latency time. This architecture improved the latency to 0.00892 ns. A Wallace tree is a high-speed multiplier that uses partial product-based mapping at different layers. This layered architecture improved the performance and reduced the latency up to 0.006873 ns. The quantum cell and bit-based processing methods were adapted by the Hasan multiplier within the Wallace tree architecture. This quantum processing-based group bit processing reduced the delay using complex architecture. This architecture achieved a latency of up to 0.002658 ns. The radix-4 multiplier was improved by integrating the Ultrafast carry in the radix-4 multiplier. This ultrafast carry-based architecture reduced the latency to 0.0018962 and effectively improved the performance of the multiplier for n-bit multiplication. The proposed lightweight component-based multiplier reduced the latency time to 0.0008962 ns. This architecture improved the efficiency and reliability of the existing multipliers.

In recent years, various component-optimized, area and power-optimized Baugh-Wooley multipliers were designed by the researchers. In this sub-section, a comparative analysis is provided against a few recent methods against latency and power dissemination parameters. Pala et al. [48] used the RTL to GDSII generation method to optimize the physical design of the multiplier. The model was incorporated with 180 nm and 45 nm technologies and optimized under timing constraints, power, and area parameters. Rampeesa et al. [49] designed a low-power 4-big Baugh wooley multiplier by integrating the approximate full adder and 1-bit mirror full adder. The model was verified on different technologies from 16 to 90 nm. The optimization was achieved under different temperature values to reduce the latency. This architecture achieved high performance with slightly high power consumption. Ponugoti et al. [50] provided a four-big Baugh-Wooley multiplier with full-swing gate diffusion and technology. The arithmetic operations were improved to improve the capabilities against different applications. This model reduced the area and number of transistors in comparison with other designs. Haridas et al. [51] provided an analytical study of the radix 2 FFT butterfly unit to optimize the multiplier. The parallel prefix was included in the multiplier to reduce the delay and power consumption. The area of design was also reduced in comparison with a traditional multiplier. Gudivada et al. [4] identified the leakage current problem and introduced the quantum dot cellular automata to optimize the performance of nanotechnologies. The energy and area-optimized 1-bit adder using QCA was integrated within the multiplier to optimize energy consumption and reduce cell count. The comparative analysis against these methods and architectures is provided under power consumption and latency parameters in Figs. 15 and 16.

Fig. 15
figure 15

Power dissipation analysis against recent Baugh Wooley multipliers

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Fig. 16
figure 16

Latency analysis against recent Baugh Wooley multipliers

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Figure 15 provides the analysis results against the power dissipation parameter. It shows that the power consumption of the model proposed by Pala et al. is a maximum of 9.342 µw. Most effective results are obtained by Ponugoti et al. and Gudivada et al. with the least power dissemination of 6.349 µw and 5.626 µw. The analysis results show that the proposed architecture reduced the power dissemination against all existing methods with the least power dissipation of 3.243 µw.

The results of the investigation against the latency parameter are presented in Fig. 16. The data indicates that the model put out by Haridas et al. has a maximum latency of 0.007321 ns. Ponugoti et al. and Gudivada et al. achieved the best outcomes with the least latency of 0.002145 ns and 0.002023 ns, respectively. The results of the analysis demonstrate that, compared to all current methods, the suggested design had the lowest latency of 0.001238.

5 Conclusion

In this paper, an improved Baugh Wooley multiplier is proposed to optimize the performance of tiny IoT devices and smart devices. The proposed architecture is integrated with a quaternary adaptive carry look-ahead adder. Functional improvement in the architecture was achieved by using the Wallace tree algorithm. The integration of the carry propagation chain within the architecture improved the performance and reduced power consumption. The use of quaternary logic within the architecture makes it suitable for small devices with high computational capability. The proposed architecture was implemented on 180 nm technology and a 1.8 W power supply. A computational evaluation was conducted on the delay and power dissipation parameters. The comparative evaluation was performed against the CLA Multiplier, Quaternary Signed Digit-based Carry Look Ahead (QSDCLA) Multiplier, Baugh Wooley Multiplier, Wallace Tree Multiplier, Hasan Multiplier, and Improved Radix Adder architectures. The analysis revealed that the latency decreased by the proposed multiplier was 0.03379 s against the CLA multiplier, 0.0155 s against the QSD CLA multiplier, 0.0080 against the Baugh-Wooley Multiplier,0.00598 against the Wallace Tree Multiplier, 0.0018 s against the Hasan Multiplier and 0.001 against the Radix-4 Multiplier. A significant performance and reliability gain is achieved under the power dissipation parameter. The proposed reduced power consumption is 7.499 w against the CLA multiplier, 6.197 w against the QSD CLA multiplier, 2.607w against the Baugh-Wooley Multiplier, 2.417 w against the Wallace Tree Multiplier, 5.267 against Hasan and 6.537w against the Radix-4 Multiplier. The comparative analysis is also provided against some of recent Baugh Wooley architecture and identified that the proposed model reduced the power dissipation and delay effectively.