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On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors

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Abstract

Novel architectures for designing modulo 2n+1 subtractors and combined adders/subtractors are proposed in this manuscript. Both the normal and the diminished-one representations of the operands are considered. Unit gate estimates and CMOS VLSI implementations reveal that the proposed modulo 2n+1 subtractors for operands in the normal representation are more efficient than those previously proposed. The proposed diminished-one modulo 2n+1 subtractors have a complexity similar to that of the corresponding diminished-one adders. Modulo 2n−1 subtractors and adders/subtractors are also considered for the sake of completeness and a comparison between alternative architectures is provided.

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Authors and Affiliations

  1. Electronics Laboratory, Physics Department, University of Patras, Patras, 26500, Greece

    E. Vassalos & D. Bakalis

  2. Computer Engineering and Informatics Department, University of Patras, Patras, Greece

    H. T. Vergos

Authors
  1. E. Vassalos
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  2. D. Bakalis
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  3. H. T. Vergos
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Correspondence to D. Bakalis.

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Vassalos, E., Bakalis, D. & Vergos, H.T. On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors. Circuits Syst Signal Process 30, 1445–1461 (2011). https://doi.org/10.1007/s00034-011-9326-5

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  • DOI: https://doi.org/10.1007/s00034-011-9326-5

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