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Dual-Miller Parallel Compensation for Low-Power Three-Stage Amplifier with a Wide Range of Capacitive Loads

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Abstract

In this paper, a dual-Miller parallel compensation (DMPC) technique for low-power three-stage amplifier is presented with detailed theoretical analysis. A feedback network realized by capacitor and transconductance is added between the first and third stage, which improves significantly the performance when driving large capacitive loads. Furthermore, it is found to be stable for a wide range of capacitive loads. The proposed DMPC amplifier has been implemented in a 0.13-μm CMOS process and the chip area is 0.17×0.11 mm2. It achieves a 0.87 MHz gain-bandwidth product by consuming a total current of 41 μA. The DMPC amplifier is verified to be stable when the load capacitor ranges from 8 pF to 2 nF.

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Acknowledgements

This work is supported by the National Nature Science Foundation of China (No. 61274027) and under Grant No. 51308020305.

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Authors and Affiliations

  1. State Key laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, 610054, P.R. China

    Pengfei Liao, Ping Luo, Shaowei Zhen & Bo Zhang

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  1. Pengfei Liao
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  2. Ping Luo
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  3. Shaowei Zhen
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  4. Bo Zhang
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Correspondence to Pengfei Liao.

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Liao, P., Luo, P., Zhen, S. et al. Dual-Miller Parallel Compensation for Low-Power Three-Stage Amplifier with a Wide Range of Capacitive Loads. Circuits Syst Signal Process 33, 287–297 (2014). https://doi.org/10.1007/s00034-013-9626-z

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  • DOI: https://doi.org/10.1007/s00034-013-9626-z

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