High-Level Power Analysis for Intellectual Property-Based Digital Systems

Abstract

Power consumption in VLSI (Very Large Scale Integration) design is becoming a mainstream issue that cannot be neglected. Low power solution for SoC (system-on-chip) flow gives designers a powerful methodology to analyze, estimate, and optimize today’s increasing power concerns.

In this paper, a new power macro-modeling technique at architectural level for the digital electronic systems is presented. This technique allows estimating the power dissipation of intellectual property (IP) components to their statistical knowledge of the primary inputs/outputs. During power estimation procedure, the sequence of an input stream is generated by a genetic algorithm (GA) using input metrics and the macro-model function is used to construct a set of functions that map the input metrics of a macro-block to its output metrics. Then, a Monte Carlo zero-delay simulation is performed for register transfer level (RTL) and the power dissipation is predicted by a macro-model function. The most important contribution of the method is that it allows fast power estimation of IP-based design by a simple addition of individual power consumption. This makes the power modeling of SoCs an easy task that permits evaluation of power features at the architectural level. In order to evaluate our model, we have constructed IP-based digital systems using different IP macro-blocks. In experiments with an individual IP macro-block, the average error is 1–2 %, and for an entire IP-based system with interconnects, the error is measured in the range of 9–15 %.