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Pulse Suppression Technique for Mitigating Digital Clock Noise

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Abstract

A practical digital clock noise mitigation technique based on pulse removal is presented. Clock frequency is increased to generate an excess pulse, which is removed in order to match the number of pulses in an average time frame. The location of the excess pulse is selected as the same time point or randomly selected in every time frame. Mathematical analyses are presented for both methods. The circuit is implemented using a state machine on a FPGA. Measurement results indicate more than 40 dB improvement on the digital noise level within a band of interest.

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Authors and Affiliations

  1. College of Engineering and Architecture, Okan University, Tuzla Kampusu, Akfirat, Tuzla, 34959, Istanbul, Turkey

    Burak Kelleci

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  1. Burak Kelleci
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Correspondence to Burak Kelleci.

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Kelleci, B. Pulse Suppression Technique for Mitigating Digital Clock Noise. Circuits Syst Signal Process 33, 1325–1336 (2014). https://doi.org/10.1007/s00034-013-9697-x

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  • DOI: https://doi.org/10.1007/s00034-013-9697-x

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