Skip to main content
SpringerLink
Log in

Analyzing the Impact of Bootstrapped ADC with Augmented NMOS Sleep Transistors Configuration on Performance Parameters

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

This paper represents an efficient bootstrapped analog to digital converter with augmented NMOS sleep transistors. The newly designed MOS-based bootstrapped circuit is implemented to provide controlled input supply for analog to digital converter to develop the enhancing capability of circuit. This will reduce the effective leakage of the circuit. In the second stage, the NMOS sleep transistors are augmented as pull-up and pull-down transistors. Due to augmentation of transistors, controlled power supply (\(V_{\mathrm{DD}})\) is obtained. Because of this, current driving capability in MOS transistors is improved and minimum sub-threshold leakage current is formed. Due to this, reduction of leakage power dissipation occurs much effectively. The whole simulation has been done at 45 nm (nanometer) technology. It is realized that the leakage power is reduced till 50 % approximately and delay performance is improved. It means that speed is improved using bootstrapped circuit with augmented sleep transistors NMOS. In this paper, different consecutive designs with Analog to Digital converter are represented.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

References

  1. M.M. Al-Ibrahim, S. Bataineh, M. Irshid, A new fast analog-to-digital counting converter, in The Third International Conference on Electronics, Circuits & Systems (ICECS), 1996, pp. 912–915

  2. M.W. Allam, M.I. Elmasry, Dynamic current mode logic (DyCML): a new low-power high-performance logic style. IEEE J. Solid State Circuits 36(3), 550–558 (2001)

    Article  Google Scholar 

  3. S. Augsburger, B. Nigolic, Combining dual-supply, dual-threshold and transistor sizing for power reduction, in IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2002, pp. 316–321

  4. H. Calhoun, A. Wang, A.P. Chandrakasan, Modeling and sizing for minimum energy operation in subthreshold circuits. IEEE J. Solid State Circuits 40(9), 1178–1186 (2005)

    Article  Google Scholar 

  5. J.C. Garcia, J.A. Montiel-Nelson, S. Nooshabadi, A single-capacitor bootstrapped power-efficient CMOS driver. IEEE Trans. Circuits Syst. II 53(9), 877–881 (2006)

    Article  Google Scholar 

  6. P. Ghafari, M. Anis, M.I. Elmasry, Impact of technology scaling on leakage reduction techniques, in IEEE Northeast Workshop on Circuit & Systems, 2007, pp. 1405–1408

  7. J.P. Halter, F.N. Najm, A gate level leakage power reduction method for ultra-low power CMOS circuits, in IEEE Custom Integrated Circuits Conference, 1997, pp. 475–478

  8. S. Hanson, M. Seok, D. Sylvester, D. Blaauw, Nanometer device scaling in sub-threshold logic and SRAM. IEEE Trans. Electron Devices 55(1), 175–185 (2008)

    Article  Google Scholar 

  9. A. Jalan, M. Khosla, Analysis of leakage power reduction techniques in digital circuits, in Annual IEEE India Conference (INDICON), 2011, pp. 1–4

  10. Y. Jincheol, K. Choi, A. Tangel, A 1-GSPS CMOS Flash A/D Converter for System-on-Chip Applications, in IEEE Computer Society Workshop on VLSI, 2001, pp. 135–139

  11. K. Jong-Woo, K. Bai-Sun, Low-voltage bootstrapped CMOS drivers with efficient conditional bootstrapping. IEEE Trans. Circuits Syst. II 55(6), 556–560 (2008)

    Article  Google Scholar 

  12. H. Kaul, D. Sylvester, in Future Performance Challenges in Nanometer Design, Design Automation Conference, 2009, pp. 3–8

  13. V. Khandelwal, A. Srivastava, Leakage control through fine-grained placement and sizing of sleep transistors, in IEEE/ACM International Conference on Computer Aided Design, 2004, pp. 533–536

  14. K.S. Khouri, N.K. Jha, Leakage power analysis and reduction during behavioral synthesis. IEEE Trans. Very Large Scale Integration Syst. 10(6), 876–885 (2002)

    Article  Google Scholar 

  15. J. Kil, G. Jie, C.H. Kim, A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting. IEEE Trans. Very Large Scale Integration Syst. 16(4), 456–465 (2008)

    Google Scholar 

  16. D. Kumar, P. Kumar, M. Pattanaik, in Performance Analysis of Dynamic Threshold MOS (DTMOS) Based 4-Input Multiplexer Switch for Low Power and High Speed FPGA Design, SBCCI’10, 2010, pp. 2–7

  17. P. Kumar, A. Kolhe, Design & implementation of low power 3-bit flash ADC in 0.18\(\mu \)m CMOS. Int. J. Soft Comput. Eng. 1(5), 71–74 (2011)

    Google Scholar 

  18. C. Law, K. Yeo, S.S. Rofail, Sub-1 V bootstrapped CMOS driver for giga-scale-integration era. Electron. Lett. 35(5), 392–394 (1999)

    Article  Google Scholar 

  19. L. Lisha, R. Sripriya, T.C. Donald, CMOS current mode logic gates for high-speed applications, in 12th NASA Symposium on VLSI Design, Coeur d’Alene, 4–5 Oct 2005

  20. J.H. Lou, J.B. Kuo, A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI. IEEE J. Solid-State Circuits 32(1), 119–121 (1997)

    Article  Google Scholar 

  21. H.P. Rajani, S. Kulkarni, Novel sleep transistor techniques for low leakage power peripheral circuits. Int. J. VLSI Des. Commun. Syst. 3(4), 81–95 (2012)

    Article  Google Scholar 

  22. M.J. Rani, S. Malarkann, Leakage power reduction and analysis of CMOS sequential circuits. Int. J. VLSI Des. Commun. Syst. 3(1), 13–23 (2012)

    Article  Google Scholar 

  23. T.C. Richards, Dynamic testing of A/D converters using the multiple coherence function. IEEE Trans. Instrum. Meas. 57(11), 2265–2272 (2006)

    Article  Google Scholar 

  24. P.S. Roy, Impact of runtime leakage reduction techniques on delay and power sensitivity under effective channel length variations, in IEEE Region 10 Conference TENCON, 2008, pp. 1–6

  25. R. Sethuram, K. Arabi, M. Abu-Rahma, Leakage power profiling and leakage power reduction using DFT hardware, in 29th IEEE VLSI Test Symposium (VTS), 2011, pp. 46–51

  26. V.K. Sharma, S. Soni, Comparison among different CMOS inverter for low leakage at different technologies. Int. J. Appl. Eng. Res. 1(2), 640–646 (2010)

    Google Scholar 

  27. K.A. Shehata, H.F. Ragai, H. Husien, Design and implementation of a high speed low power 4-bit Flash ADC, in International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2007, pp. 200–203

  28. A.K. Singh, Digital VLSI Design, Eastern Economy Edition (PHI Publications, New Delhi, 2011)

    Google Scholar 

  29. T. Taun, B. Lai, Leakage power analysis of a 90 nm FPGA, in IEEE Custom Integrated Circuits Conference, 2003, pp. 57–60

  30. S. Veeramachanen, A.M. Kumar, V. Tummala, M.B. Srinivas, Design of a low power, variable-resolution flash ADC, in 22nd International Conference on VLSI Design, 2009, pp. 117–122

  31. N. Verma, A.P. Chandrakasan, A 65 nm 8T sub-Vt SRAM employing sense-amplifier redundancy, in Proc. ISSCC Dig. Tech. Papers, 2007, pp. 328–606

  32. A. Wang, A. Chandrakasan, A 180-mV subthreshold FFT processor using a minimum energy design methodology. IEEE J. Solid State Circuits 40(1), 310–319 (2005)

    Article  Google Scholar 

  33. N.H.E. Waste, K. Eshraghian, Principles of CMOS Design A System Perspective, 2nd edn. (Pearson/DK Publishing, Upper Saddle River/London, 2000)

    Google Scholar 

  34. M. Wei-Hsiang, J.C. Kao, V.S. Sathe, M.C. Papaefthymiou, 187 MHz sub-threshold-supply charge-recovery FIR. IEEE J. Solid State Circuits 45(4), 793–803 (2010)

    Article  Google Scholar 

  35. C.J. Woong, C.Y.R. Chen, A novel leakage power reduction technique for CMOS circuit design, in SoC Design Conference (ISOCC), 2010, pp. 119–122

  36. G. Yeap, Practical Low Power Digital VLSI Design (Kluwer Academic Publishers, Norwell, 1998)

    Book  Google Scholar 

  37. H. Yingchieh, C. Chiachi, S. Chauchin, Design of a subthreshold-supply bootstrapped CMOS inverter based on an active leakage-current reduction technique. IEEE Trans. Circuits Syst. II 59(1), 55–59 (2012)

    Article  Google Scholar 

Download references

Acknowledgments

This exertion was supported by ITM University Gwalior in collaboration with Cadence System Design, Bangalore.

Author information

Authors and Affiliations

  1. ITM University, Gwalior, India

    Prateek Jain

  2. ECED, ITM University, Gwalior, India

    Shyam Akashe

Authors
  1. Prateek Jain
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Shyam Akashe
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Prateek Jain.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Jain, P., Akashe, S. Analyzing the Impact of Bootstrapped ADC with Augmented NMOS Sleep Transistors Configuration on Performance Parameters. Circuits Syst Signal Process 33, 2009–2025 (2014). https://doi.org/10.1007/s00034-013-9736-7

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-013-9736-7

Keywords

Search

Navigation