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Novel Analog Calibration Technique for Current-Steering DACs

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Abstract

This paper presents a novel high-speed area-efficient analog calibration technique for current-steering (CS) digital-to-analog converters (DACs). Negative feedback is used to correct errors caused due to mismatch, process variation, temperature, or aging. A faster calibration cycle and smaller additional circuits are possible with analog calibration, compared to the more prevalent digital calibration techniques. The new calibration circuit is presented with the necessary theoretical details. To demonstrate this technique, a 10-bit binary-weighted CS DAC is implemented in a \(0.18\, \upmu \hbox {m}\) CMOS process. With worst-case process parameter variations, simulated integral and differential nonlinearities of the calibrated DAC are less than \(\pm 0.32\) LSB. The DAC occupies an area of approximately \(0.3\,\hbox {mm}^{2}\).

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Authors and Affiliations

  1. Electronics and Communication Department, Dharmsinh Desai University, Nadiad, 387 001, India

    Pallavi G. Darji

  2. Institute of Engineering and Technology, Ahmedabad University, Ahmedabad, 380 009, India

    Chetan D. Parikh

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  1. Pallavi G. Darji
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  2. Chetan D. Parikh
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Correspondence to Pallavi G. Darji.

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Darji, P.G., Parikh, C.D. Novel Analog Calibration Technique for Current-Steering DACs. Circuits Syst Signal Process 34, 2407–2418 (2015). https://doi.org/10.1007/s00034-015-9979-6

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  • DOI: https://doi.org/10.1007/s00034-015-9979-6

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