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A Filter Bank Mismatch Calibration Technique for Frequency-Interleaved ADCs

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Abstract

The filter bank mismatch of analog analysis filters in frequency-interleaved ADCs (FI-ADCs) degrades the system’s spurious-free dynamic range (SFDR) significantly. In this paper, a calibration approach for compensating such mismatch is presented. By modeling the parameter mismatches in the analysis filters, the filter bank mismatch compensation is divided into a coarse trimming mode and a fine-tuning mode. After the coarse trimming mode by trimming the resistors and capacitors in analog domain, the fine-tuning mode by updating coefficients of synthesis filters is further carried out in digital domain to achieve high-precision calibration. A design example of 10 GS/s 8-bit four-channel FI-ADC is built in MATLAB. The simulation results show that 25-tap synthesis filters could satisfy the reconstruction requirement of 8-bit ADC. The proposed calibration technique improves the SFDR to 51 dB, compensating the filter mismatch effectively.

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Authors and Affiliations

  1. The School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, Singapore

    Lei Qiu, Yuanjin Zheng & Liter Siek

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  1. Lei Qiu
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  2. Yuanjin Zheng
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  3. Liter Siek
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Correspondence to Lei Qiu.

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Qiu, L., Zheng, Y. & Siek, L. A Filter Bank Mismatch Calibration Technique for Frequency-Interleaved ADCs. Circuits Syst Signal Process 35, 3847–3862 (2016). https://doi.org/10.1007/s00034-016-0252-4

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