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New Designs for Reduced-Redundancy Transceivers

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Abstract

Block-based transceivers are widely used in wireless communication systems, mostly due to their well-defined structure and blockwise encoding. Interblock interference caused by superpositions of delayed signal copies is among their main physical-layer challenges, which is commonly eliminated with redundancy between adjacent data-blocks. Besides, channel equalization is also employed to further mitigate multipath channel interferences. The chosen amount of redundancy, however, may be overestimated, which opens an opportunity for reduced-redundancy superfast transceivers, whose key features include high spectral efficiency and low computational cost. Although superfast approaches aim at low complexity, proper equalizer-coefficient design and update procedures are still very intricate tasks, and most approaches are rather computationally cumbersome. This paper addresses such problem by proposing a new design strategy for reduced-redundancy block-based transceivers, which provides semi-blind equalization with data-selective update, in addition to the possibility of using redundant parallel equalizer structures, which are based on the use of fast Fourier transforms and one-tap equalizers. Simulation results indicate that the proposed methodology is effective and also able to achieve a performance comparable to what is obtained with state-of-the-art techniques, depending on the target application.

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Acknowledgments

This work was made possible through grants from CNPq, Capes, Fapeam, and Faperj, which are Brazilian research councils.

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Authors and Affiliations

  1. IEMN-IRCICA, 50 Avenue du Halley, 59650, Villeneuve-d’Ascq, France

    Mauro L. de Freitas

  2. Electrical Engineering Program of Federal University of Amazonas (UFAM), Manaus, AM, 69077-000, Brazil

    Mauro L. de Freitas, Eddie B. de Lima Filho & Waldir S. da Silva Júnior

  3. Department of Electronics and Computer Engineering (DEL/Poli), Electrical Engineering Program (PEE/COPPE) of Federal University of Rio de Janeiro, Rio de Janeiro, RJ, 21941-972, Brazil

    Wallace A. Martins

  4. FPF Tech, Avenida Gov. Danilo de Matos Areosa, 1170, Manaus, AM, 69075-351, Brazil

    Eddie B. de Lima Filho

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  1. Mauro L. de Freitas
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  2. Wallace A. Martins
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  3. Eddie B. de Lima Filho
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  4. Waldir S. da Silva Júnior
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Correspondence to Eddie B. de Lima Filho.

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de Freitas, M.L., Martins, W.A., de Lima Filho, E.B. et al. New Designs for Reduced-Redundancy Transceivers. Circuits Syst Signal Process 36, 2075–2101 (2017). https://doi.org/10.1007/s00034-016-0400-x

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