Abstract
This study presents the design and implementation of a compact and wideband active variable true-time delay line for timed array applications. Using a combination of coarse delay cells and fine delay cells, the proposed delay line achieves a large delay range and a high delay tuning resolution. Instead of LC delay lines or transmission lines, the delay can be approximated by compact active filters using transconductors and capacitors. The coarse delay cell adopts inductive peaking to broaden the bandwidth, and the fine delay cell employs a novel differential active inductor to improve the delay resolution and integration level. The group delays of the coarse delay cells and fine delay cells are analyzed and optimized. The signal transmission path is controlled by path-selection amplifiers and V–I conversion switches to achieve delay variability. The delay time is calibrated by the delay-locked loop (DLL) to mitigate the process, voltage and temperature variations. The complementary metal-oxide-semiconductor (CMOS) variable true-time delay line is fabricated in a 0.18-\(\upmu \hbox {m}\) CMOS process. Experiments indicate that the maximal relative delay is 95 ps and that the delay resolution is 5 ps within a 10% delay variation over a frequency range of 0.6–4.2 GHz. The chip dissipates 88 mW under a 1.8-V supply, and the core area including the DLL circuit is only 0.05 \(\hbox { mm}^{2}\).
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References
E. Adabi, A.M. Niknejad, Broadband variable passive delay elements based on an inductance multiplication technique, in IEEE Radio Frequency Integrated Circuits Symposium, (2008), pp. 445–448
K. Bult, H. Wallinga, A CMOS analog continuous-time delay line with adaptive delay-time control. IEEE J. Solid State Circuits 23(3), 759–766 (1988)
Z. Cao, Q. Ma, A.B. Smolders, Y. Jiao et al., Advanced integration techniques on broadband millimeter-wave beam steering for 5G wireless networks and beyond. IEEE J. Quantum Electron. 52(1), 1–20 (2016)
Y. Chen, W. Li, An ultra-wideband pico-second true-time-delay circuit with differential tunable active inductor. Analog Integr. Circuits Signal Process. 91(1), 9–19 (2017)
Y. Chen, Z. Wang et al., Low-jitter PLL based on symmetric phase-frequency detector technique. Analog Integr. Circuits Signal Process. 62(1), 23–27 (2010)
Y.W. Chia, T.H. Lim, J.K. Yin, P.Y. Chee, S.W. Leong, C.K. Sim, Electronic beam-steering design for UWB phased array. IEEE Trans. Microw. Theory Tech. 54(6), 2431–2438 (2006)
T.S. Chu, H. Hashemi, A true time-delay-based bandpass multi-beam array at mm-waves supporting instantaneously wide bandwidths, in IEEE International Solid-State Circuits Conference, (2010), pp. 38–39
T.S. Chu, J. Roderick, H. Hashemi, An integrated ultra-wideband timed array receiver in \(0.13\,\mu \text{ m }\) CMOS using a path-sharing true time delay architecture. IEEE J. Solid State Circuits 42(12), 2834–2850 (2008)
J. Duan, Z. He, Doppler radar by using single multicarrier pulse based on optical fibre delay lines. J. Syst. Eng. Electron. 21(3), 404–407 (2010)
Y. Gao, Y. Zheng, S. Diao et al., An integrated beamformer for IR-UWB receiver in 0.18-\(\mu \)m CMOS, in IEEE International Symposium on Circuits and Systems, (2011), pp. 1548–1551
S.K. Garakoui, E.A.M. Klumperink, B. Nauta, F.E. Van Vliet, Time delay circuits: a quality criterion for delay variations versus frequency, in IEEE International Symposium on Circuits and Systems, (2010), pp. 4281–4284
S.K. Garakoui, E.A.M. Klumperink, B. Nauta, F.E. Van Vliet, A 1-to-2.5 GHz phased-array IC based on gm-RC all-pass time-delay cells, in IEEE International Solid-State Circuits Conference, (2012), pp. 80–82
S.K. Garakoui, E.A.M. Klumperink, B. Nauta, F.E. Van Vliet, Frequency limitations of first-order all-pass delay circuits. Circuits Syst. II Express Br. IEEE Trans. 60(9), 572–576 (2013)
S.K. Garakoui, E.A.M. Klumperink, B. Nauta, F.E. Van Vliet, Compact cascadable \(\text{ g }_{{\rm m}}\)-C all-pass true time delay cell with reduced delay variation over frequency. IEEE J. Solid State Circuits 50(3), 693–703 (2015)
L. He, W. Li, N. Li, J. Ren, A 24-GHz novel true-time-delay phase shifter utilizing negative group delay compensation, in Phased Array Systems and Technology (PAST), IEEE International Symposium on 2016, (2016), pp. 18–21
C. Jiang, A. Mostajeran, R. Han, M. Emadi, H. Sherry, A. Cathelin, E. Afshari, A fully integrated 320 GHz coherent imaging transceiver in 130 nm SiGe BiCMOS. IEEE J. Solid State Circuits 51(11), 2596–2609 (2016)
X. Li, S. Shekhar, D.J. Allstot, GM-boosted common-gate LNA and differential Colpitts VCO/QVCO in 0.18-\(\mu \)m CMOS. IEEE J. Solid State Circuits 40(12), 2609–2619 (2005)
F.R. Liao, S.S. Luc, A programmable edge-combining DLL with a current-splitting charge pump for SPUR suppression. Circuits Syst. II Express Br. IEEE Trans. 57(12), 946–950 (2011)
L.H. Lu, H.H. Hsieh, Y.T. Liao, A wide tuning-range CMOS VCO with a differential tunable active inductor. IEEE Trans. Microw. Theory Tech. 54(9), 3462–3468 (2006)
Q. Ma, D.M.W. Leenaerts, P.G.M. Baltus, Silicon-based true-time-delay phased-array front-ends at Ka-band. IEEE Trans. Microw. Theory Tech. 63(9), 2942–2952 (2015)
M. Maeng, F. Bien, Y. Hur, H. Kim, 0.18-\(\mu \)m CMOS equalization techniques for 10-Gb/s fiber optical communication links. Microw. Theory Tech. IEEE Trans. 53(11), 3509–3519 (2005)
R. Navid, E.H. Chen, M. Hossain, B. Leibowitz, J. Ren, C.H.A. Chou, A 40 Gb/s serial link transceiver in 28 nm CMOS technology. IEEE J. Solid State Circuits 50(4), 814–827 (2015)
J. Roderick, H. Krishnaswamy, K. Newton, H. Hashemi, Silicon-based ultra-wideband beam-forming. IEEE J. Solid State Circuits 41(8), 1726–1739 (2006)
B. Razavi, Design of Analog CMOS Integrated Circuits (McGraw-Hill, New York, 2001)
Y.H. Tu, K.H. Cheng, H.Y. Wei, H.Y. Huang, A low jitter delay-locked-loop applied for DDR4, in IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, (2013), pp. 98–101
C. Wijenayake, Y. Xu, A. Madanayake et al., RF analog beamforming fan filters using CMOS all-pass time delay approximations. Circuits Syst. I Regul. Pap. IEEE Trans. 59(5), 1061–1073 (2012)
J.H. Zhan, K. Maurice, J. Duster, K.T. Kornegay, Analysis and design of negative impedance LC oscillators using bipolar transistors. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 50(11), 1461–1464 (2003)
Acknowledgements
This work is supported by the National Natural Science Foundation of China (No. 61471119). The authors wish to thank Wei Li and Li Zhang for their technical instructions.
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Chen, Y., Li, W. Compact and Broadband Variable True-Time Delay Line with DLL-Based Delay-Time Control. Circuits Syst Signal Process 37, 1007–1027 (2018). https://doi.org/10.1007/s00034-017-0594-6
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DOI: https://doi.org/10.1007/s00034-017-0594-6