Abstract
With the leakage power becoming a most important concern in deep sub-micron designs, the advent of FinFET offers promising options due to its superior electrical properties and design flexibility. To support the VLSI digital system design flow based on the standard cells in FinFET, the building method of optimized FinFET standard cells is proposed. This method is derived on the basis of jointly optimizing the back-gate voltages and the width to length ratio of the transistors in the stacked structure in each standard cell under the premise of maintaining the performance. By employing this design method, optimized standard cells are generated and form a low-power high-performance standard cell library. Simulation results of the standard cells designed with our proposed method demonstrate that the leakage power can be reduced by a factor of 47.99 at most while the worst-case delay can achieve a maximum reduction of 10.17%. Monte Carlo simulation results illustrate that the optimized cells can gain more dependability to process variations and environmental changes. The 16-bit ripple carry adder implemented with this optimized FinFET library can obtain a maximum leakage power reduction of 59.6% and a worst-case delay reduction of 21.8%.
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References
M. Agostinelli, M. Alioto, D. Esseni, Leakage-delay tradeoff in FinFET logic circuits: a comparative analysis with bulk technology. IEEE Trans. Very Large Scale Integr. Syst. 18(2), 232–245 (2010)
M. Alioto, Comparative evaluation of layout density in 3T, 4T, and MT FinFET standard cells. IEEE Trans. Very Large Scale Integr. Syst. 19(5), 751–762 (2011)
D. Baccarin, D. Esseni, M. Alioto, Low-standby current 4T FinFET buffers: analysis and evaluation below 45 nm. in Proceedings of 2010 IEEE International Conference on Microelectronics, (2010), pp. 296–299
D. Baccarin, D. Esseni, M. Alioto, A novel back-biasing low-leakage technique for FinFET forced stacks. in Proceedings of IEEE International Symposium on Circuits and Systems, (2011) pp. 2079–2082
D. Baccarin, D. Esseni, M. Alioto, Mixed FBB/RBB: a novel low-leakage technique for FinFET forced stacks. IEEE Trans. Very Large Scale Integr. Syst. 20(8), 1467–1472 (2012)
Y. Cao, S. Sinha (Nanoscale Integration and Modeling (NIMO) Group, ASU), Predictive Technology Model. http://ptm.asu.edu/ (2012)
Y.K. Choi, K. Asano, N. Lindert, V. Subramanian, Ultra-thin body SOI MOSFET for deep-sub-tenth micron era. IEEE Electron. Device Lett. 21(5), 254–255 (2000)
X.X. Cui, K.S .Ma, K. Liao, N. Liao, A dynamic-adjusting threshold-voltage scheme for FinFETs low power designs. in Proceedings of IEEE International Symposium on Circuits and Systems, (2013), pp. 129–132
C. Gallon, C. Fenouillet-Beranger, A. Vandooren, F. Boeuf, Ultra-thin fully depleted SOI devices with thin BOX, ground plane and strained liner booster. in Proceedings of 2006 IEEE International SOI Conference, (2006), pp. 17–18
M.C. Johnson, D. Somasekhar, K. Roy, Leakage control with efficient use of transistor stacks in single threshold CMOS. in Proceedings of the 36th annual ACM/IEEE Design Automation Conference, (1999), pp. 442–445
K. Liao, X.X. Cui, N. Liao, K.S. Ma, Leakage power reduction of adiabatic circuits based on FinFET devices. IEICE Trans. Electron. 96(8), 1068–1075 (2013)
K. Liao, X.X. Cui, N. Liao, K.S. Ma, D. Wu, W. Wei et al., Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs. Sci. China Inf. Sci. 57(4), 1–13 (2014)
K. Liao, X.X. Cui, N. Liao, T. Wang, Design of D flip-flops with low power-delay product based on FinFET. in 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), (2014), pp. 1–3
N. Liao, X.X. Cui, K. Liao, K.S. Ma, D. Wu, W. Wei et al., Low power adiabatic logic based on FinFETs. Sci. China Inf. Sci. 57(2), 1–13 (2014)
S. Narendra, V. De, D. Antoniadis, Scaling of stack effect and its application for leakage reduction. in Proceedings of the 2001 International Symposium on Low Power Electronics and Design ACM, (2001), pp. 195–200
S. Narendra, V. De, S. Borkar, D.A. Antoniadis, Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-\(\mu \)m CMOS. IEEE J. Solid-State Circ. 39(3), 501–510 (2004)
J.W. Tschanz, S.G. Narendra, Y. Ye, B. Bloechel, S. Borkar, V. De, Dynamic sleep transistor and body bias for active leakage power control of microprocessors. IEEE J. Solid-State Circ. 38(11), 1838–1845 (2003)
E. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.Y. Yang, et al., FinFET scaling to 10 nm gate length. in Proceedings of 2002 IEEE International Electron Devices Meeting, (2002), pp. 251–254
Acknowledgements
This work was supported by Beijing Natural Science Foundation (Grant No. 4152020), National Natural Science Foundation of China (Grant No. 61306040), State Key Development Program for Basic Research of China (973) (Grant No. 2015CB057201), Natural Science Foundation of Guangdong Province, China (Grant No. 2015A030313147) and the R&D project of Shenzhen Government, China (Grant Nos. JCYJ20170412150411676, JCYJ20160229122349365).
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Wang, T., Cui, X., Liao, K. et al. Design of Low-Power High-Performance FinFET Standard Cells. Circuits Syst Signal Process 37, 1789–1806 (2018). https://doi.org/10.1007/s00034-017-0646-y
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DOI: https://doi.org/10.1007/s00034-017-0646-y