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A High-Speed VLSI Architecture for Motion Estimation Using Modified Adaptive Rood Pattern Search Algorithm

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Abstract

The paper presents an efficient VLSI architecture for fast Motion Estimation in video codec using modified Adaptive Rood Pattern Search Algorithm. The proposed architecture uses an interleaved memory arrangement and an early check technique to compute the Sum of Absolute Differences. The proposed design can process High Definition (1080p) video frames in real time while optimizing the hardware area. The architecture has been implemented in verilog HDL and mapped to 45 nm FPGA. It uses only 6.8K gates for the implementation of the datapath and the controller. It achieves a maximum frequency of 120 MHz. However, working at 100 MHz, it is able to process 60 HD (\(1920\times 1080\)) frames per second while consuming 39 mW of power. The proposed architecture achieves premium speed with an optimum power and area requirements and can be suitably incorporated in light-weight video-intensive devices like smart-phones, tablet computers.

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Authors and Affiliations

  1. Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, 721302, India

    Baishik Biswas, Rohan Mukherjee, Indrajit Chakrabarti & Ajoy Kumar Ray

  2. Department of Electrical Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, 721302, India

    Pranab Kumar Dutta

Authors
  1. Baishik Biswas
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  2. Rohan Mukherjee
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  3. Indrajit Chakrabarti
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  4. Pranab Kumar Dutta
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  5. Ajoy Kumar Ray
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Correspondence to Baishik Biswas.

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Biswas, B., Mukherjee, R., Chakrabarti, I. et al. A High-Speed VLSI Architecture for Motion Estimation Using Modified Adaptive Rood Pattern Search Algorithm. Circuits Syst Signal Process 37, 4548–4567 (2018). https://doi.org/10.1007/s00034-018-0778-8

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  • DOI: https://doi.org/10.1007/s00034-018-0778-8

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