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Analysis of Noise Immunity for Wide OR Footless Domino Circuit Using Keeper Controlling Network

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Abstract

Due to high-speed and low area, domino circuits are used in a variety of applications such as comparator, adder, MUX, memory, microprocessor, and adder. In this paper, we propose a keeper controlling network to improve the noise immunity and performance for wide fan-in OR footless domino circuit. In the proposed design, the keeper controlling network controls the keeper transistor. The network itself consists of an NMOS transistor, which acts as a switch and inverter chain. This network turns OFF the keeper transistor at the start of evaluation phase to enhance the speed of the domino circuit. Similarly, it turns ON the keeper transistor, when all inputs are at low voltage in the evaluation phase to enhance the noise immunity. We simulate the proposed design and other existing circuits using 90 nm CMOS technology on HSPICE. The simulation results show that the proposed design considerably reduces delay, power consumption, power delay product, and improves unity noise gain as compared to the HS-domino circuit for 32-inputs OR gate.

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References

  1. A.K. Agarwal, S. Wairya, R.K. Nagaria, S. Tiwari, Mixed gate diffusion input full adder topology for high speed low power digital circuits. World Appl. Sci. J. 7, 138–144 (2009)

    Google Scholar 

  2. C.J. Akl, A. Magdy, A. Bayoumi, Single-phase SP-Domino: a limited-switching dynamic circuit technique for low-power wide fan-in logic gates. IEEE Trans. Circuits Syst. 55(2), 141–145 (2008)

    Google Scholar 

  3. A. Alvandpour, R. Krishnamurthy, K. Sourrty, S.Y. Borkar, A sub-130nm conditional-keeper technique. IEEE Trans. Solid State Circuits 37, 633–638 (2002)

    Article  Google Scholar 

  4. A. Amirabadi, A. Chehelcheraghi, S.H. Rasouli, A. Seyedi, K.A. Afzai, Low power and high performance clock delayed domino logic using saturated keeper, in Proceeding of ISCAS (2006), pp. 3173–3176

  5. M.H. Anis, M.W. Allam, M.I. Elmasry, Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies. IEEE Trans. Very Large Scale Integr. VLSI Syst. 10(2), 71–78 (2002)

    Article  Google Scholar 

  6. F.H. Asgari, M. Ahmadi, J. Wu, Low power high performance keeper technique for high fan-in dynamic gates, in Proceedings of European Conference on Circuit Theory and Design (ECCTD) (2009), pp. 523–526

  7. R.J. Barkar, CMOS: Circuit Design, Layout, and Simulation (Wiley, New York, 2011)

    Google Scholar 

  8. Berkeley Predictive Technology Model (BPTM). http://www.device.eecs.berkeley.edu/wptm/ download.htm

  9. S.R. Chawdhary, A. Banerjee, A. Roy, H. Saha, A high speed 8 transistors full adder design using 3 transistor XOR computer engineering. Int. J. Electr. Comput. Eng. 3(12), 784–790 (2008)

    Google Scholar 

  10. W. Chiu, H.R. Lin, A conditional isolation technique for low-energy and high-performance wide domino gates, in IEEE Proceedings of TENCON (2007), pp. 1–4

  11. M. Elgebaly, M. Sachdev, A leakage tolerant energy efficient wide domino circuit technique, in Proceeding of the 45th Midwest Symposium on Circuits and Systems (MWSCAS), vol. 1 (2002), pp. 487–490

  12. F. Frustaci, P. Corsonello, G. Cocorullo, A new noise-tolerant dynamic logic circuit design, in Proceedings of Research in Microelectronics and Electronics Conference (PRIME) (2007), pp. 233–236

  13. N. Gong, B. Guo, Analysis and optimization of leakage current characteristics in sub-65nm dual-\(\text{ V }_{{\rm t}}\) footed domino circuits. Microelectron. J. 39, 1149–1155 (2008)

    Article  Google Scholar 

  14. T.K. Gupta, K. Khare, Lector with footed-diode inverter: a technique for leakage reduction in domino circuits. Circuit Syst. Signal Process. 32(6), 2707–2722 (2013)

    Article  Google Scholar 

  15. R.G.D. Jeyasingh, N. Bhat, B. Amrutur, Adaptive keeper design for dynamic logic circuits using rate sensing technique. IEEE Trans. Very Large Scale Integr. VLSI Syst. 19, 295–304 (2011)

    Article  Google Scholar 

  16. S.O. Jung et al., Skew-tolerant high speed (STHS) domino logic. Proc. ISCAS 4, 154–157 (2001)

    Google Scholar 

  17. J.T. Kao, A.P. Chandrakasan, Dual-threshold voltage techniques for low power digital circuits. IEEE Trans. Solid-State Circuits 35(7), 1009–1018 (2000)

    Article  Google Scholar 

  18. V. Kursun, E.G. Friedman, Sleep switch dual threshold voltage domino logic with reduced standby leakage current. IEEE Trans. Very Large Scale Integr. VLSI Syst. 12(5), 485–496 (2000)

    Article  Google Scholar 

  19. O. Kwang, L. Kim, A clock delayed sleep mode domino logic for wide dynamic OR gate, in Proceedings in ISLPED (2003), pp. 176–179

  20. Y. Lih, N. Tzartzanis, W.W. Walker, A leakage current replica keeper for dynamic circuits. IEEE J. Solid State Circuits 42, 48–55 (2007)

    Article  Google Scholar 

  21. Z. Liu, V. Kursun, Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current. Microelectron. J. 37, 812–820 (2006)

    Article  Google Scholar 

  22. Z. Liu, V. Kursun, PMOS-only sleep switch dual-threshold voltage domino logic in sub-65-nm CMOS technologies. IEEE Trans. Very Large Scale Integr. VLSI Syst. 15(12), 1311–1319 (2007)

    Article  Google Scholar 

  23. Z. Liu, V. Kursun, Leakage power characteristics of dynamic circuits in nanometer CMOS technologies. IEEE Trans. Circuits Syst. 53(8), 692–696 (2006)

    Article  Google Scholar 

  24. H.M. Meimand, K. Roy, Diode-footed domino: a leakage-tolerant high fan-in dynamic circuits design style. IEEE Trans. Circuits Syst. 51, 495–503 (2004)

    Article  Google Scholar 

  25. A. Mohammad, A new leakage-tolerant domino circuit using voltage comparison for wide fan-in gates in deep sub-micron technology. Integr. VLSI J. 51, 61–71 (2015)

    Article  Google Scholar 

  26. F. Moradi, T.V. Cao, E.I. Vatajelu, A. Peiravi, H. Mahmoodi, D.T. Wisland, Domino logic designs for high-performance and leakage-tolerant applications. VLSI J. 46, 247–254 (2013)

    Article  Google Scholar 

  27. K.J. Nowke, T. Galambos, Circuits design techniques for gigahertz integer microprocessor, in IEEE International conference on computer design (1998), pp. 11–16

  28. A. Peiravi, M. Asyaei, Current comparison-based domino: new low leakage high speed domino circuit for wide fan-in gates. IEEE Trans. Very Large Scale Integr. VLSI Syst. 21(5), 934–943 (2013)

    Article  Google Scholar 

  29. S.M. Sharroush, Y.S. Abdalla, A.A. Dessouki, A.E. Badawy, Speeding-up wide-fan in domino logic using a controlled strong PMOS keeper, in Proceeding of the International conference on Computer and Communication Engineering (2008), pp. 633–637

  30. S.M. Sharroush, Y.S. Abdalla, A.A. Dessouki, E.A. Badawy, Compensating for the keeper current of CMOS domino logic using a well designed NMOS transistor, in Proceedings of 26thNational Radio Science Conference (NRSC2009) (2009), pp. 1–8

  31. J. Wang, W. Wu, N. Gong, L. Hou, Domino gate with modified voltage keeper, in Proceedings of 11th International Symposium on Quality Electronic Design (2010), pp. 443–446

  32. H. Xue, S. Ren, Low power-delay-product dynamic CMOS circuit design techniques. Electron. Lett. IET 53(5), 302–304 (2017)

    Article  Google Scholar 

  33. H. Yeganeh, A.H. Darvishan, A. Amirabadi, Noise tunable clock delayed domino logic using latched keeper, in IEEE International Conference on Microelectronics (ICM) (2007), pp. 187–190

  34. P. Zhao, B. Magdy, G. Pradeep, K. Weidong, A low power domino with differential-controlled keeper, in Proceeding of IEEE (2007), pp. 1625–1628

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Authors and Affiliations

  1. Department of Applied Science, Rajkiya Engineering College, Ambedkar nagar, Akbarpur, Uttar Pradesh, 224122, India

    Amit Kumar Pandey

  2. Department of Electronics and Communication, Dr. B.R. Ambedkar National Institute of Technology, Jalandhar, Punjab, 144011, India

    Pawan Kumar Verma

  3. Department of Electronics and Communication, Raj Kumar Goel Institute of Technology and Management, Ghaziabad, India

    Rajesh Verma

  4. Department of Electronics and Communication, Maulana Azad National Institute of Technology, Bhopal, India

    Tarun Kumar Gupta

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  1. Amit Kumar Pandey
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  2. Pawan Kumar Verma
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  4. Tarun Kumar Gupta
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Correspondence to Amit Kumar Pandey.

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Pandey, A.K., Verma, P.K., Verma, R. et al. Analysis of Noise Immunity for Wide OR Footless Domino Circuit Using Keeper Controlling Network. Circuits Syst Signal Process 37, 4599–4616 (2018). https://doi.org/10.1007/s00034-018-0781-0

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  • DOI: https://doi.org/10.1007/s00034-018-0781-0

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