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Novel Optimum Parity-Preserving Reversible Multiplier Circuits

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Abstract

Reversible logic is considered as a basic requirement for designing quantum computers. Reversible circuits do not waste energy. The use of this logic in low-power complementary metal–oxide–semiconductor circuits, quantum computing, and DNA computing has rendered reversible logic integral in today’s technology. Multiplication is regarded as a major operation in the arithmetic. Herein, four optimized parity-preserving reversible signed and unsigned multiplier circuits are presented to reduce the QUANTUM COST of the circuits. The designs can be expanded to an N × N dimension. We prove that these multiplier circuits have lower QUANTUM COST, CONSTANT INPUTs, and GARBAGE OUTPUTs compared with previous studies.

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Acknowledgements

The authors would like to thank Prof. Nader Bagherzadeh, Eng. Elika Navi, and Eng. Pegah Foroutan for their contribution.

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Authors and Affiliations

  1. Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

    Ehsan PourAliAkbar & Midia Reshadi

  2. Faculty of Computer Science and Engineering, Shahid Beheshti University G. C., Tehran, Iran

    Keivan Navi

  3. Department of Computer Engineering, Yadegar -e- Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran

    Majid Haghparast

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  1. Ehsan PourAliAkbar
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  2. Keivan Navi
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  3. Majid Haghparast
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  4. Midia Reshadi
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Correspondence to Keivan Navi.

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PourAliAkbar, E., Navi, K., Haghparast, M. et al. Novel Optimum Parity-Preserving Reversible Multiplier Circuits. Circuits Syst Signal Process 39, 5148–5168 (2020). https://doi.org/10.1007/s00034-020-01406-w

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  • DOI: https://doi.org/10.1007/s00034-020-01406-w

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