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Two Behavioural Error Detection Techniques for the Cascaded Integrator–Comb Interpolation Filter Implemented on FPGA

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Abstract

The cascaded integrator–comb (CIC) filter is a key building block for communication and sample rate conversion systems that require efficient implementation. One such example is in satellite applications. Space applications have the problem of being highly susceptible to cosmic radiation, which in turn has the possibility of corrupting data. It is therefore necessary to devise techniques that detect errors with as little resource usage as possible in order to meet the usually strict constraints in space applications. Presented in this paper are two techniques derived from studying the behaviour of the interpolation version of the filter. The first being a parallel prediction technique improves upon DMR in terms of resource usage and offers very close error protection coverage. The second offers a trade-off of resource utilisation against error detection.

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Authors and Affiliations

  1. ARIES Research Center, Universidad Antonio de Nebrija, C/Pirineos, 55, 28040, Madrid, Spain

    Kyle W. Gear, Alfonso Sánchez-Macián, Francisco Garcia-Herrero & Juan Antonio Maestro

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  1. Kyle W. Gear
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  2. Alfonso Sánchez-Macián
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  3. Francisco Garcia-Herrero
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  4. Juan Antonio Maestro
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Correspondence to Kyle W. Gear.

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Gear, K.W., Sánchez-Macián, A., Garcia-Herrero, F. et al. Two Behavioural Error Detection Techniques for the Cascaded Integrator–Comb Interpolation Filter Implemented on FPGA. Circuits Syst Signal Process 39, 5529–5542 (2020). https://doi.org/10.1007/s00034-020-01418-6

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  • DOI: https://doi.org/10.1007/s00034-020-01418-6

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