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A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time

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Abstract

The design of active delay circuits and variable delay elements is being investigated over the years as they are popular inside the integrated circuit chip, for example in on-chip clock distribution. The function of these kinds of circuit is to transfer the input signal at the output with an added amount of timing delay. For clock signals, it is important to achieve equal rise/fall time in order to support correct level-triggered-based on-chip sequential operation. However, most of the variable delay elements are unable to impart the matching of output rise/fall time. Therefore, in this article, we have unearthed a delay circuit which is expected to generate nearly equal rise/fall time at the output having a unique setup of delivering variable delay. A small-signal model for this proposed circuit is presented to note the related parameters for achieving the near-symmetric output rise/fall time. The circuit has been simulated in Cadence Virtuoso\(^{\textregistered }\) for 90 nm Process Design Kit with an input signal of 1 GHz at 1.1 V power supply \((V_{\mathrm{dd}})\). The simulation results assure that the expected functionality of our proposed variable delay architecture is sustained under different corner variations.

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Data Availability

Raw data were generated at Integrated Circuit & System Lab, NIT Arunachal Pradesh. Derived data supporting the findings of this study are available from the corresponding author [Dr. Alak Majumder majumder.alak@gmail.com] on request.

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Acknowledgements

We cordially like to thank Dr. Abir J. Mondal (Department of Electronics & Communication Engineering, NIT Arunachal Pradesh) and Dr. Debjit Dutta (Department of Basic & Applied Science, NIT Arunachal Pradesh) for sharing their technical insights. Also, it is our immense pleasure to thank Mr. Supriyo Srimani (School of VLSI, IIEST Shibpur) for helping us in the content writing.

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Authors and Affiliations

  1. Integrated Circuit and System Lab, Department of Electronics and Communication Engineering, National Institute of Technology (NIT), Arunachal Pradesh, Yupia, India

    Pritam Bhattacharjee & Alak Majumder

  2. Research Engineer I, Packaging Research Center Georgia Institute of Technology, Atlanta, GA, 30332, USA

    Bidyut K. Bhattacharyya

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  1. Pritam Bhattacharjee
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  2. Bidyut K. Bhattacharyya
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  3. Alak Majumder
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Correspondence to Alak Majumder.

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This work was supported by MEITy (Grant No. 9(1)/2014-MDD), Govt. of India under Visvesvaraya PhD Scheme & SMDP-C2SD project.

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Bhattacharjee, P., Bhattacharyya, B.K. & Majumder, A. A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time. Circuits Syst Signal Process 40, 1569–1588 (2021). https://doi.org/10.1007/s00034-020-01546-z

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