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An FPGA Implementation of the Log-MAP Algorithm for a Dirty Paper Coding CODEC

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Abstract

This work describes the log-MAP (BCJR) algorithm implementation of a close to capacity dirty paper coding CODEC. The CODEC consists of eight deep pipeline processors. It decodes blocks of 975 bits in 26.9 ms using less than 9.7% of low-cost FPGA (and no DSP blocks). Two pipelines, for alpha and beta, calculate the values of gamma (of the BCJR) to reduce the storage requirements. The final log-likelihood ratio (LLR) is calculated together with alpha, reusing intermediate results. The number of bits used by the different signals of the processor is easily configurable. It was set to six bits to the channel measure signals and eight bits to log of probability signals like alpha, beta, and others. The CODEC clock was 100 MHz. The achieved bit rate is 36.2 Kbps per CODEC, but multiple CODECs can be fit into a single chip. The CODEC is 3.49 dB from the channel capacity.

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References

  1. L. Bahl, J. Cocke, F. Jelinek, J. Raviv, Optimal decoding of linear codes for minimizing symbol error rate (corresp). IEEE Trans. Inf. Theory 20(2), 284–287 (1974)

    Article  Google Scholar 

  2. M. Barrenechea, L. Barbero, M. Mendicute, J. Thompson, Design and hardware implementation of a low-complexity multiuser vector precoder, in Conference on Design and Architectures for Signal and Image Processing (DASIP) (IEEE, New York, 2010), pp. 160–167

  3. S. Belfanti, C. Roth, M. Gautschi, C. Benkeser, Q. Huang, A 1 Gbps LTE-advanced turbo-decoder ASIC in 65 nm CMOS, in Symposium on VLSI Circuits (VLSIC) (IEEE, New York, 2013), pp. C284–C285

  4. P. Bhagawat, W. Wang, M. Uppal, G. Choi, Z. Xiong, M. Yeary, A. Harris, An FPGA implementation of dirty paper precoder, in International Conference on Communications. ICC’07 (IEEE, New York, 2007), pp. 2761–2766

  5. Y. Chen, D. Hocevar, A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder, in Global Telecommunications Conference, GLOBECOM’03, vol. 1 (IEEE, New York, 2003), pp. 113–117

  6. C.L. Chen, K.S. Lin, H.C. Chang, W.C. Fang, C.Y. Lee, A 11.5-Gbps LDPC decoder based on CP-PEG code construction, in Proceedings of ESSCIRC’09 (IEEE, New York, 2009), pp. 412–415

  7. M. Costa, Writing on dirty paper (corresp.). IEEE Trans. Inf. Theory 29(3), 439–441 (1983)

    Article  Google Scholar 

  8. U. Erez, S. Ten Brink, A close-to-capacity dirty paper coding scheme. IEEE Trans. Inf. Theory 51(10), 3417–3432 (2005)

    Article  MathSciNet  Google Scholar 

  9. U. Erez, R. Zamir, Achieving 1/2 log (1 + SNR) on the AWGN channel with lattice encoding and decoding. IEEE Trans. Inf. Theory 50(10), 2293–2314 (2004)

    Article  Google Scholar 

  10. A. Giulietti, B. Bougard, L. Van Der Perre, Turbo Codes: Desirable and Designable (Springer, Berlin, 2012)

    Google Scholar 

  11. A. Goldsmith, S.A. Jafar, N. Jindal, S. Vishwanath, Capacity limits of MIMO channels. IEEE J. Sel. Areas Commun. 21(5), 684–702 (2003)

    Article  Google Scholar 

  12. J. Hagenauer, E. Offer, L. Papke, Iterative decoding of binary block and convolutional codes. IEEE Trans. Inf. Theory 42(2), 429–445 (1996)

    Article  Google Scholar 

  13. S. Hu, F. Rusek, A generalized zero-forcing precoder with successive dirty-paper coding in MISO broadcast channels. IEEE Trans. Wirel. Commun. 16(6), 3632–3645 (2017)

    Article  Google Scholar 

  14. T. Ilnseher, F. Kienle, C. Weis, N. Wehn, A 2.15 Gbit/s turbo code decoder for LTE advanced base station applications, in 7th International Symposium on Turbo Codes and Iterative Information Processing (ISTC) (IEEE, New York, 2012), pp. 21–25

  15. A. Jovicic, P. Viswanath, Cognitive radio: an information-theoretic perspective. IEEE Trans. Inf. Theory 55(9), 3945–3958 (2009)

    Article  MathSciNet  Google Scholar 

  16. Y. Jung, C. Chung, J. Kim, Y. Jung, 7.7 Gbps encoder design for IEEE 802.11 n/ac QC-LDPC codes, in International SoC Design Conference (ISOCC) (IEEE, New York, 2012), pp. 215–218

  17. T. Kim, K. Kwon, J. Heo, Practical dirty paper coding schemes using one error correction code with syndrome. IEEE Commun. Lett. 21(6), 1257–1260 (2017)

    Article  Google Scholar 

  18. A. Li, L. Xiang, T. Chen, R.G. Maunder, B.M. Al-Hashimi, L. Hanzo, VLSI implementation of fully parallel LTE turbo decoders. IEEE Access 4, 323–346 (2016)

    Article  Google Scholar 

  19. H.A. Loeliger, An introduction to factor graphs. IEEE Signal Process. Mag. 21(1), 28–41 (2004)

    Article  Google Scholar 

  20. P.A.C. Lopes, DPC in VHDL on GitHub (2020). http://github.com/paclopes/DPC

  21. K. Manjunatha, V.A. Meshram, Design and FPGA implementation of power efficient turbo decoder for 4G LTE standards. Int. J. Appl. Eng. Res. 12(21), 10921–10925 (2017)

    Google Scholar 

  22. M.M. Mansour, N.R. Shanbhag, VLSI architectures for SISO-APP decoders. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 11(4), 627–650 (2003)

    Article  Google Scholar 

  23. R.G. Maunder, A fully-parallel turbo decoding algorithm. IEEE Trans. Commun. 63(8), 2762–2775 (2015)

    Article  MathSciNet  Google Scholar 

  24. T.T. Nguyen-Ly, V. Savin, K. Le, D. Declercq, F. Ghaffari, O. Boncalo, Analysis and design of cost-effective, high-throughput LDPC decoders. IEEE Trans Very Large Scale Integr (VLSI) Syst 26(3), 508–521 (2017)

    Article  Google Scholar 

  25. K.M. Rege, K. Balachandran, J.H. Kang, M.K. Karakayali, Practical dirty paper coding with sum codes. IEEE Trans. Commun. 64(2), 441–455 (2015)

    Article  Google Scholar 

  26. W. Ren, H. Ren, The design and implementation of high-speed codec based on FPGA, in 10th International Conference on Communication Software and Networks (ICCSN) (IEEE, New York, 2018), pp. 427–532

  27. P. Robertson, E. Villebrun, P. Hoeher, A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain, in International Conference on Communications, ICC’95, vol. 2 (IEEE, New York, 1995), pp. 1009–1013

  28. A.D. Sarwate, M. Gastpar, Arbitrarily dirty paper coding and applications, in International Symposium on Information Theory (IEEE, New York, 2008), pp. 925–929

  29. S. Shao, P. Hailes, T.Y. Wang, J.Y. Wu, R.G. Maunder, B.M. Al-Hashimi, L. Hanzo, Survey of turbo, LDPC, and polar decoder ASIC implementations. IEEE Commun. Surv. Tutor. 21(3), 2309–2333 (2019)

    Article  Google Scholar 

  30. S. Ten Brink, Convergence of iterative decoding. Electron. Lett. 35(13), 1117–1119 (1999)

    Google Scholar 

  31. S. Ten Brink, G. Kramer, Design of repeat-accumulate codes for iterative detection and decoding. IEEE Trans. Signal Process. 51(11), 2764–2772 (2003)

    Article  MathSciNet  Google Scholar 

  32. Y. Tong, VHDL implementation of turbo codec. Ph.D. Thesis, University of Ottawa (Canada) (2003)

  33. M. Uppal, G. Yue, Y. Xin, X. Wang, Z. Xiong, A dirty-paper coding scheme for the cognitive radio channel, in International Conference on Communications (IEEE, New York, 2010), pp. 1–5

  34. A.J. Viterbi, An intuitive justification and a simplified implementation of the MAP decoder for convolutional codes. IEEE J. Sel. Areas Commun. 16(2), 260–264 (1998)

    Article  Google Scholar 

  35. A.J. Viterbi, J.K. Omura, Principles of Digital Communication and Coding (Courier Corporation, New York, 2013)

    MATH  Google Scholar 

  36. C.Y. Yang, M.K. Ku, LDPC coded OFDM modulation for high spectral efficiency transmission, in 4th European Conference on Circuits and Systems for Communications, ECCSC (IEEE, New York, 2008), pp. 280–284

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Acknowledgements

This work was supported by national funds through Fundação para a Ciência e a Tecnologia (FCT) with reference UIDB/50021/2020.

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  1. INESC-ID - Instituto de Engenharia de Sistemas e Computadores, Investigação e Desenvolvimento em Lisboa, Rua Alves Redol n.9, 1000-029, Lisbon, Portugal

    Paulo A. C. Lopes & José A. B. Gerald

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  2. José A. B. Gerald
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Correspondence to Paulo A. C. Lopes.

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Lopes, P.A.C., Gerald, J.A.B. An FPGA Implementation of the Log-MAP Algorithm for a Dirty Paper Coding CODEC. Circuits Syst Signal Process 40, 1905–1925 (2021). https://doi.org/10.1007/s00034-020-01567-8

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