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A Low-Complexity Sparse LMS Algorithm Optimized for Hardware Implementation

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Abstract

A novel sparse LMS algorithm for the sparse system identification is proposed to reduce the complexity of the existing algorithms. The proposed algorithm discards W(n) when the value of the current weight vector is within a certain range. The algorithm also optimizes the iterative update equation by using only the product term to calculate the value of W(n+1). The hardware implementation shows that the total logic elements number of the proposed algorithm is 60.06% less than the latest l0-ILMS algorithm, while the performance is nearly the same.

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Data Availability

The data used to support the findings of this study are available from the corresponding author upon request.

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Acknowledgements

This work is supported by the Chongqing Scientific Project under grant No. cstc2021ycjh-bgzxm0085, No. cstc2019jscx-msxmX0079 and No. cstc2021jscx-rhcxzy0042. The authors thank Mr. Xiaodong Ma for his help of hardware implementation assistance.

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Authors and Affiliations

  1. Key Laboratory of Micro-Electronic Engineering, Chongqing University of Posts and Telecommunications, Chongqing, 40065, China

    Jin Meng, Hongsheng Zhang, Shenghong Yi, Ting Liu, Jizhang Gan & Hong Yang

  2. School of Electronic Information and Communication, Huazhong University of Science and Technology, Wuhan, 430074, China

    Jin Meng

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  1. Jin Meng
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  2. Hongsheng Zhang
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  3. Shenghong Yi
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Correspondence to Hongsheng Zhang or Ting Liu.

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Meng, J., Zhang, H., Yi, S. et al. A Low-Complexity Sparse LMS Algorithm Optimized for Hardware Implementation. Circuits Syst Signal Process 42, 971–995 (2023). https://doi.org/10.1007/s00034-022-02152-x

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