An optimal emulator and VLSI layout for complete binary trees

Abstract.

How complex does a graph need to be in order to emulate an arbitrary size complete binary tree with the same level of efficiency as would be obtained by a directed complete graph? In this paper, this question is answered by showing that any $N=2^n$-node graph needs to have at least ${3N-2\over 2}$ edges in order to perform this emulation. Subsequently, a graph is presented which meets this bound, and it is shown how to optimally embed an arbitrary size complete binary tree in the proposed graph. It is also shown how to optimally embed a $kN$ node cycle in the proposed graph of $N$ nodes with unit dilation, unit congestion and uniform load of $k$. Finally optimal VLSI layouts are presented for the proposed graph which require asymptotically same area as the corresponding layouts for complete binary trees.