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Defect-Tolerance in Cellular Nanocomputers

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Abstract

For the manufacturing of computers built by nanotechnology, defects are expected to be a major problem. This paper explores this issue for nanocomputers based on cellular automata. Known for their regular structure, such architectures promise cost-effective manufacturing based on molecular self-organization. We show how a cellular automaton can detect defects in a self-contained way, and how it configures circuits on its cells while avoiding the defects. The employed cellular automaton is asynchronous, i.e., it does not require a central clock to synchronize the updates of its cells. This mode of timing is especially suitable for the high integration densities of nanotechnology implementations, since it potentially causes less heat dissipation.

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References

  1. Biafore, M., “Cellular Automata for Nanometer-scale Computation,” Physica D, 70, pp. 415-433, 1994.

  2. Cunningham, J. A., “The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing,” IEEE Transaction on Semiconductor Manufacturing, 3, 2, pp. 60-71, 1990.

  3. Dalal, Y. K. and Metcalfe, R. M., “Reverse Path Forwarding of Broadcast Packets,” Communications of the ACM, 21, 12, pp. 1040-1048, 1978.

  4. Durbeck, L. J. K. and Macias, N. J., “The Cell Matrix: An Architecture for Nanocomputing,” Nanotechnology, 12, pp. 217-230, 2001.

  5. Goldstein, S. C. and Budiu, M., “NanoFabrics: Spatial Computing Using Molecular Electronics,” in Proc. of the 28th Annual International Symposium on Computer Architecture, pp. 178-191, 2001.

  6. Han, J. and Jonker, P., “A ddefect- and fault-tolerant Architecture for Nanocomputers,” Nanotechnology, 14, pp. 224-230, 2003.

  7. Heath, J. R., Kuekes, P. J., Snider, G. S., and Williams, R. S., “A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology,” Science, 280, pp. 1716-1721, 1998.

  8. Isokawa, T., Abo, F., Peper, F., Adachi, S., Lee, J., Matsui, N., and Mashiko, S., “Fault-tolerant Nanocomputers based on Asynchronous Cellular Automata,” International Journal of Modern Physics D, 15, 6, pp. 893-915, 2004.

  9. Isokawa, T., Abo, F., Peper, F., Kamiura, N., and Matsui, N., “Defect-tolerant Computing based on an Asynchronous Cellular Automaton,” in Proc. of SICE Annual Conference, pp. 1746-1749, 2003.

  10. Kuekes, P. J., Robinett, W., Seroussi, G., and Williams, R. S., “Defect-tolerant Interconnect to Nanoelecronic Circuits: Internally Redundant Demultiplexers based on Error-correcting Codes,” Nanotechnology, 16, pp. 869-881, 2005.

  11. Lee, J., Peper, F., Adachi, S., Morita, K., and Mashiko, S., “Reversible Computation in Asynchronous Cellular Automata,” in Proc. of the Third International Conference on Unconventional Models of Computation 2002, Springer, pp. 220-229. 2002

  12. Mishra, M., and Goldstein, S. C., “Defect Tolerance at the End of the Roadmap,” in Proc. of the IEEE International Test Conference (ITC), 1, pp. 1201-1210, 2003

  13. Morita, K., “A Simple Universal Logic Element and Cellular Automata for Reversible Computing,” LNCS, 2055, Springer pp.102-113, 2003.

  14. Patwardhan, J. P., Dwyer, C., Lebeck, A. R., “Design and Evaluation of Fail-Stop Self-Assembled Nanoscale Processing Elements,” in Proc. of 2nd IEEE International Workshop on Defect and Fault Tolerant Nanoscale Architectures (NanoArch 2006), 2006.

  15. Peper, F., Isokawa, T., Kouda, N., and Matsui, N., “Self-Timed Cellular Automata and their Computational Ability,” Future Generation Computer Systems, 18, pp. 893-904, 2002.

  16. Peper, F., Lee, J., Abo, F., Isokawa, T., Adachi, S., Matsui, N., and Mashiko, S., “Fault-Tolerance in Nanocomputers: A Cellular Array Approach,” IEEE Transaction on Nanotechnology, 3, 1, pp. 187-201, 2004.

  17. Peper, F., Lee, J., Adachi, S., and Mashiko, S., “Laying out Circuits on Asynchronous Cellular Arrays: A Step towards Feasible Nanocomputers?,” Nano-technology, 14, pp. 469-485, 2003.

  18. Sadek, A. S., Nikolic, K., and Forshaw, M., “Parallel Information and Computation with Restitution for Noise-tolerant Nanoscale Logic Networks,” Nano-technology, 15, pp. 192-210, 2004.

  19. Stapper, C. H., Armstrong, F. M., and Saji, K., “Integrated Circuit Yield Statistics,” Proc. of the IEEE, 71, 4, pp. 453-470, 1983.

  20. Takada, Y., Isokawa, T., Peper, F., and Matsui, N., “Universal Construction and Self-Reproduction on Self-Timed Cellular Automata,” International Journal of Modern Physics C, 17, 7, pp. 985-1007, 2006.

  21. Wang, T., Bennaser, M., Guo, Y., and Moritz, C. A., “Combining Circuit Level and System Level Techniques for Defect-Tolerant Nanoscale Architectures,” in Proc. of 2 nd International Workshop on Defect and Fault Tolerant Nanoscale Auchitecutures (NanoArch 2006), 2006.

  22. Zhang, R., Li, J. F., and Viehland, D., “Self-assembly of Point Defects into Clusters and Defect-free Regions: A Simulation Study of Higher-valent Substituted Ferroelectric Perovskites,” Computational Materials Science, 29, 1, pp. 67-75, 2004.

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Correspondence to Teijiro Isokawa.

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A short version of this paper was presented at the IEEE-Nano Conf. on 12 July, 2005 in Nagoya, Japan.

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Isokawa, T., Kowada, S., Takada, Y. et al. Defect-Tolerance in Cellular Nanocomputers. New Gener. Comput. 25, 171–199 (2007). https://doi.org/10.1007/s00354-007-0010-z

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  • DOI: https://doi.org/10.1007/s00354-007-0010-z

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