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Booting clock synchronization in partially synchronous systems with hybrid process and link failures

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Abstract

This paper provides description and analysis of a new clock synchronization algorithm for synchronous and partially synchronous systems with unknown upper and lower bounds on delays. It is purely message-driven, timer-free and relies on a hybrid failure model incorporating both process and link failures, in both time and value domain. Unlike existing solutions, our algorithm works during both system start-up and normal operation: Whereas bounded precision (the mutual deviation of any two clocks) can always be guaranteed, accuracy (clocks being within a linear envelope of real-time) and hence progress is only ensured when sufficiently many correct processes are eventually up and running. By means of a detailed analysis, we provide formulas for resilience, precision and envelope bounds.

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Authors and Affiliations

  1. Embedded Computing Systems Group (E182/2), Technische Universität Wien, Treitlstraße 3, 1040, Vienna, Austria

    Josef Widder & Ulrich Schmid

  2. Laboratoire d’Informatique LIX, Ecole Polytechnique, 91128, Palaiseau Cedex, France

    Josef Widder

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  1. Josef Widder
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  2. Ulrich Schmid
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Correspondence to Josef Widder.

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This work has been supported by the Austrian START programme Y41-MAT, the BM:vit FIT-IT Embedded Systems project DCBA (proj.no. 808198), and the FWF project Theta (proj.no. P17757-N04).

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Widder, J., Schmid, U. Booting clock synchronization in partially synchronous systems with hybrid process and link failures. Distrib. Comput. 20, 115–140 (2007). https://doi.org/10.1007/s00446-007-0026-0

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