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Signal-integrity improvement method and its robustness evaluation for VLSI and VLSI-packaging

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Abstract

Nowadays, a GHz frequency signal needs to be propagated on a printed circuit board (PCB) with low distortions. In addition, a higher-frequency signal of 10 GHz or more will also need to be propagated with low distortion in very-large-scale integration (VLSI) in the future. However, signal propagation with low distortion is getting more and more difficult as the frequency increases. In order to solve this problem and to ensure signal integrity, we have proposed a novel transmission line called a “segmental transmission line” (STL). In the STL, a transmission line is divided into multiple segments of individual characteristic impedance. The multiple segments are designed to fix the waveform distortion on the transmission line by solving a combinatorial explosion problem using a genetic algorithm. In a previous article, we have shown the effectiveness of an STL designed for a GHz clock signal in computer simulations. We have also fabricated two scaled-up STL prototypes for a clock signal using real printed circuit boards (PCBs). In this article, we input a random signal by changing its frequency to the scaled-up STL prototype designed for a 150-MHz clock signal. We show that the STL has high robustness to the random signals and the frequency fluctuations, which indicates the generality of the STL technique.

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References

  1. Naono N, Nakamura Y (2001) Details on high-speed digital system design. NikkeiBP

  2. Taguchi M (1994) High-speed, small-amplitude I/O interface circuit for memory bus application. IEICE Trans Electron E77-C(12): 1944–1950

    Google Scholar 

  3. Yasunaga M, Yoshihara I (2005) The segmental transmission line and its design methodology: line trace ensuring high signal integrity in VLSI mounting boards. Trans Inst Electron Inf Commun Eng D-I J88-D-I(5):915–929

    Google Scholar 

  4. Nakayama H, Yasunaga M, Yamaguchi Y, et al (2008) Experimental verification of improved signal integrity using the segmental transmission line. 70th National Convention of the Information Processing Society of Japan, Tsukuba, No. 1, pp 9–10

  5. Nakayama H, Shimauchi Y, Aibe N, et al (2009) A high signal integrity transmission line for high-speed VLSI packaging: proposal and prototype evaluation. DA Symposium 2009, pp 187–192

  6. Melanie M, Iba H (1997) An introduction to genetic algorithms. Tokyo Denki University Press

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Correspondence to Moritoshi Yasunaga.

Additional information

This work was presented in part at the 15th International Symposium on Artificial Life and Robotics, Oita, Japan, February 4–6, 2010

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Ishiguro, M., Nakayama, H., Shimauchi, Y. et al. Signal-integrity improvement method and its robustness evaluation for VLSI and VLSI-packaging. Artif Life Robotics 15, 325–329 (2010). https://doi.org/10.1007/s10015-010-0819-2

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  • DOI: https://doi.org/10.1007/s10015-010-0819-2

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