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Towards closing the specification gap by integrating algorithm-level and system-level design

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Abstract

Modern multiprocessor system-on-chip (MPSoC) designs face challenges in tremendous complexity imposed by the wide range of functional and architectural requirements. Design automation methodologies address some of the complexity through design abstractions from two different angles, namely functionality and architecture. Algorithm-level design (ALD), such as Simulink, focuses on managing the functional complexity through algorithm modeling. Meanwhile, system-level design (SLD) addresses the platform complexity by exploring and synthesizing architecture models from specifications captured in a system-level design language (SLDL). However, these two design methodologies are inherently disjoint as they focus on different design domains at separate abstraction levels. As a result, transition from algorithm models to system-level explorations often requires re-authoring of the functional SLDL specification to expose hierarchy and parallelism. This thus forms the Specification Gap causing a loss of productivity and stalling the overall design cycle. This paper proposes to join ALD and SLD to close the specification gap through a Specification Synthesis approach. We introduce Algo2Spec, which synthesizes an SLDL specification out of an algorithm model in Simulink. Algo2Spec enables a rapid heterogeneous Design Space Exploration while still tuning the algorithm according to functional needs. With Algo2Spec, system level design principles propagate up to higher abstraction levels and a new joint algorithm/architecture co-design flow is created. The joint flow seamlessly spans from algorithm modeling down to heterogeneous implementations crossing multiple abstractions. Our approach empowers designers to create, simulate, and explore models in a rapid design cycle. Utilizing the joint flow, we demonstrate opportunities for algorithm and architecture co-design on a set of real-world benchmark applications ranging from 57 to 5733 Simulink blocks. The automatic synthesis avoids the tedious and error-prone manual conversion of Simulink algorithm models into SLDL specifications. Algo2Spec executes in 4.5 s on average to synthesize a single Simulink block to a fully functional SLDL behavior. Compared to an estimated 5.18 h of manual editing, Algo2Spec improves productivity by three orders of magnitude for obtaining the system-level specifications from Simulink models.

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Notes

  1. We chose SCE since the system-level exploration environment is readily available. The concepts are applicable to other SLDE, such as PeaCE.

  2. For the purpose of this paper, we have chosen SpecC [25] as the SLDL. The principles and concepts, however, are equally transferable to other SLDL, such as SystemC.

  3. Classes are an abstract representation of behaviors and channel [23].

  4. In the rest of the paper, we will use Behaviors to denote elements in the SLDL. The concept is equivalent to modules or blocks.

  5. Complex signals in Simulink are currently not supported such as non-virtual buses.

  6. A Simulink solver computes the next simulation time with an interval called step size.

  7. SIR is primarily the internal representation of the SpecC SLDL, however producing SystemC have also been shown in [54].

  8. Algo2Spec currently does not support pipelined execution.

References

  1. Abdi S, Gajski D (2006) Verification of system level model transformations. Int J Parallel Program 34(1):29–59

    Article  MATH  Google Scholar 

  2. Altintas I, Berkley C, Jaeger E, Jones M, Ludascher B, Mock S (2004) Kepler: an extensible system for design and execution of scientific workflows. In: Proceedings of the 16th international conference on scientific and statistical database management, pp 423–424

  3. Baleani M, Ferrari A, Mangeruca L, Sangiovanni-vincentelli AL, Freund U, Schlenker E, J. Wolff H (2005) Correct-by-construction transformations across design environments for modelbased embedded software development. In: Proceedings of the conference on design, automation and test in Europe (DATE)

  4. Boland JF, Thibeault C, Zilic Z (2005) Using MATLAB and simulink in a SystemC verification environment. In: Proceedings of design and verification conference, DVCon

  5. Cai L, Gerstlauer A, Gajski DD (2004) Retargetable profiling for rapid, early system-level design space exploration. In: Proceedings of the design automation conference (DAC). San Diego, CA

  6. Cai L, Gerstlauer A, Gajski DD (2005) Multi-metric and multi-entity characterization of applications for early system design exploration. In: Proceedings of the Asia and South Pacific design automation conference (ASPDAC). Shanghai, China

  7. Cain J, McCrindle R (2002) An investigation into the effects of code coupling on team dynamics and productivity. In: Proceedings of the 26th annual international computer software and applications conference (COMPSAC 2002). pp 907–913

  8. Caspi P, Curic A, Maignan A, Sofronis C, Tripakis S, Niebert P (2003) From simulink to scade/lustre to tta: A layered approach for distributed embedded applications. In: Proceedings of the 2003 ACM SIGPLAN conference on language, compiler, and tool for embedded systems, LCTES ’03. ACM, New York, NY, USA, pp 153–162

  9. Chandraiah P, Dömer R (2005) Specification and design of a MP3 audio decoder. Technical Report CECS-TR-05-04, University of California, Irvine

  10. Chandraiah P, Dömer R (2008) Code and data structure partitioning for parallel and flexible MPSoC specification using designer-controlled recoding. IEEE Trans Comput-Aided Des Integr Circuits Syst 27(6):1078–1090

    Article  Google Scholar 

  11. Chaturvedi DK (2009) Modeling and simulation of systems using Matlab/Simulink, pp 1–733

  12. Dassault (2013) Dymola dynamic modeling laboratory, dymola release notes

  13. Dmer R, Gerstlauer A, Peng J, Shin D, Cai L, Yu H, Abdi S, Gajski DD (2008) System-on-chip environment: a SpecC-based framework for heterogeneous MPSoC design 2008, 5, 15: 13

  14. Dömer R (1999) The SpecC internal representation. Technical report, Information and Computer Science, University of California, Irvine. SpecC V 2.0.3

  15. Dömer R (2010) Computer-aided recoding for multi-core systems. In: Design automation conference (ASP-DAC), 2010 15th Asia and South Pacific, pp 713–716

  16. Dömer R, Zhu J, Gajski DD (1998) The SpecC language reference manual. Technical report, SpecC Technology Open Consortium

  17. GmbH DsPaCe (2004) Guide. TargetLink Production Code Generation. V2.0

  18. Eker J, Janneck J, Lee E, Liu J, Liu X, Ludvig J, Neuendorffer S, Sachs S, Xiong Y (2003) Taming heterogeneity-the ptolemy approach. Proc IEEE 91(1):127–144

    Article  Google Scholar 

  19. Ellsberger J, Hogrefe D, Sarma A (1997) SDL: formal object-oriented language for communicating systems. Prentice Hall, New Jersey

    Google Scholar 

  20. ETAS: Ascet. http://www.etas.de. In: online

  21. Gajski D, Vahid F, Narayan S, Gong J (1998) SpecSyn: an environment supporting the specify-explore-refine paradigm for Hardware/Software system design. IEEE Trans VLSI Syst 6:84–100

    Article  Google Scholar 

  22. Gajski DD (1997) Principles of digital design. Prentice Hall, New Jersey

    Google Scholar 

  23. Gajski DD, Zhu J, Dömer R, Gerstlauer A, Zhao S (2000) SpecC: specification language and design methodology. Kluwer Academic Publishers, Basel

    Book  Google Scholar 

  24. Gall DL (1991) MPEG: a video compression standard for multimedia applications. Commun ACM 34:46–58

    Article  Google Scholar 

  25. Gerstlauer A, Dömer R, Peng J, Gajski DD (2001) System design: a practical guide with SpecC. Kluwer Academic Publishers, Basel

    Book  Google Scholar 

  26. Gerstlauer A, Zhao S, Gajski D, Horak A (2000) SpecC system-level design methodology applied to the design of a GSM vocoder. In: Proceedings of the workshop of synthesis and system integration of mixed information technologies

  27. Ghosh A, Ratasuk R, Mondal B, Mangalvedhe N, Thomas T (2010) Lte-advanced: next-generation wireless broadband technology [invited paper]. Wireless Commun IEEE 17(3):10–22

    Article  Google Scholar 

  28. Gruttner K, Hylla K, Rosinger S, Nebel W (2010) Towards an esl framework for timing and power aware rapid prototyping of hw/sw systems. In: Proceedings of the specification design languages (FDL 2010), 2010 Forum on, pp 1–6

  29. Ha S, Lee C, Yi Y, Kwon S, Joo YP (2006) Hardware-software codesign of multimedia embedded systems: the peace. In: Proceedings of the 12th IEEE international conference, embedded and real-time computing systems and applications, 2006, pp 207–214

  30. Han SI, Chae SI, Brisolara L, Carro L, Popovici K, Guerin X, Jerraya AA, Huang K, Li L, Yan X (2009) Simulink-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation. Integration, the VLSI Journal 42(2):227–245

    Article  Google Scholar 

  31. Hochstein L, Carver J, Shull F, Asgari S, Basili V, Hollingsworth J, Zelkowitz M (2005). Parallel programmer productivity: a case study of novice parallel programmers. In: Supercomputing, 2005. Proceedings of the ACM/IEEE SC 2005 conference, pp 35–35

  32. Johnson GW (1997) LabVIEW Graphical Programming: Practical Applications in Instrumentation and Control, 2nd edn. McGraw-Hill, McGraw-Hill School Education Group

    Google Scholar 

  33. Kienhuis B, Rijpkema E, Deprettere E (2000) Compaan: deriving process networks from matlab for embedded signal processing architectures. In: Proceedings of the eighth international workshop on hardware/software codesign, 2000. CODES 2000, pp 13–17

  34. Marchioro G, Daveau JM, Jerraya A (1997) Transformational partitioning for co-design of multiprocessor systems. In: 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997. Digest of Technical Papers, pp 508–515

  35. Martin G, Mueller W (2005) UML for SOC Design. Springer, Dordrecht

    Book  Google Scholar 

  36. The MathWorks Inc (1993) Natick. MATLAB and Simulink, MA

  37. The MathWorks Inc: Simulink embedded coder reference R2011b (2011)

  38. The Mathworks Inc: Untimed SystemC/TLM Simulation (2012b)

  39. Mellor SJ, Balcer MJ (2002) Executable UML: a foundation for model-driven architecture, 1st edn. Addison-Wesley Professional, New York

    Google Scholar 

  40. Mueller W, Dömer R, Gerstlauer A (2002) The formal execution semantics of SpecC. In: Proceedings of the international symposium on system synthesis. Kyoto, Japan

  41. Nacci AA, Rana V, Bruschi F, Sciuto D, Beretta I, Atienza D (2013) A high-level synthesis flow for the implementation of iterative stencil loop algorithms on fpga devices. In: Proceedings of the 50th annual design automation conference, DAC ’13, pp. 52:1–52:6. ACM, New York, NY, USA

  42. Open SystemC Initiative (2000) Functional specification for systemC 2.0

  43. Popinchalk S, Glass J, Shenoy R, Aberg R (2007) Working in teams: Modeling and control design within a single software environment

  44. Popovici K (2008) Multilevel programming environment for heterogeneous MPSoC architectures. PhD, Institut National Polytechnique de Grenoble, Grenoble

  45. Posadas H, Herrera F, Sanchez P, Villar E, Blasco F (2004) System-level performance analysis in systemc. In: Proceedings of the design, automation and test in Europe conference and exhibition, 2004. vol. 1, pp 378–383

  46. Riccobene E, Scandurra P, Rosti A, Bocchio S (2005) A SoC design methodology involving a UML 2.0 profile for SystemC. In: Design, automation, and test in Europe, pp 704–709

  47. Sangiovanni-Vincentelli A, Martin G Platform-based design and software design methodology for embedded systems 18(6), 23–33

  48. Schirrmeister F, Sangiovanni-Vincentelli A (2001) Virtual component co-design-applying function architecture co-design to automotive applications. In: Proceedings of the IEEE international vehicle electronics conference, 2001. IVEC 2001. pp 221–226

  49. Shin D, Gerstlauer A, Domer R, Gajski D (2008) An interactive design environment for c-based high-level synthesis of rtl processors. Very Large Scale Integr (VLSI) Syst IEEE Trans 16(4):466–475

    Article  Google Scholar 

  50. Sullivan C, Wilson A, Chappell S (2004) Using c based logic synthesis to bridge the productivity gap. In: Proceedings of the 2004 Asia and South Pacific design automation conference, ASP-DAC ’04, p 349354. IEEE Press, Piscataway, NJ, USA

  51. Thompson M, Nikolov H, Stefanov T, Pimentel A, Erbas C, Polstra S, Deprettere E (2007) A framework for rapid system-level exploration, synthesis, and programming of multimedia mp-socs. In: Proceedings of the 5th IEEE/ACM/IFIP International Conference Hardware/Software codesign and system synthesis (CODES+ISSS), 2007, pp. 9–14

  52. Tripakis S, Sofronis C, Caspi P, Curic A (2005) Translating discrete-time simulink to lustre. ACM Trans Embed Comput Syst 4(4):779–818

    Article  Google Scholar 

  53. Vanderperren Y, Dehaene W (2006) From UML/SysML to Matlab/Simulink: current state and future perspectives. In: Proceedings of the design, automation and test in Europe, 2006. DATE ’06. vol. 1, pp 1–1

  54. Viskic I, Dömer R (2006) A flexible, syntax independent representation (SIR) for system level design models. In: Proceedings of the 9th EUROMICRO Conference on, digital system design: architectures, methods and tools, 2006. DSD 2006. p 288294

  55. Wakabayashi K, Okamoto T (2000) C-based SoC design flow and EDA tools: an ASIC and system vendor perspective. IEEE Trans Comput Aided Des Integr Circuits Syst 19(12):1507–1522

    Article  Google Scholar 

  56. Wiegand T, Sullivan GJ, Bjontegaard G, Luthra A (2003) Overview of the h. 264/avc video coding standard. Circuits and systems for video technology. IEEE Trans 13(7):560–576

    Google Scholar 

  57. Wood W, Kleb W (2003) Exploring xp for scientific research. Software, IEEE 20(3):30–36

    Article  Google Scholar 

  58. Yu H, Dömer R, Gajski D (2004) Embedded software generation from system level design languages. In: Proceedings of the Asia and South pacific design automation conference (ASPDAC). Yokohama, Japan

  59. Zeigler BP, Praehofer H, Kim TG (2000) Theory of modeling and simulation: integrating discrete event and continuous complex dynamic systems. Academic press, Cypress

    Google Scholar 

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Acknowledgments

The work presented in this paper is partially supported by the National Science Foundation under Grant No. 1136027.

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  1. Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA

    Jiaxing Zhang & Gunar Schirner

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Correspondence to Jiaxing Zhang.

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Zhang, J., Schirner, G. Towards closing the specification gap by integrating algorithm-level and system-level design. Des Autom Embed Syst 19, 389–419 (2015). https://doi.org/10.1007/s10617-015-9161-1

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