Functional verification of power gated designs by compositional reasoning

Abstract

Power gating is a technique for low power design in which whole sections of the chip are powered off when they are not needed, and powered back on when they are. Functional correctness of power gating is usually checked at the system level, where the most widely used technique is simulation using pseudo-random stimuli. This normally entails running extremely expensive ternary simulations, in order to model the memory loss that occurs as a result of a memory element being powered off. We propose instead a methodology in which we prove sequential equivalence between the power gated design and a simplified version of itself, then use the simplified version in a binary simulation. We use a compositional approach that looks for partial equivalence of each unit under a suitable set of assumptions, guaranteed by the neighboring units. The partial equivalences are then composed into total equivalence on the whole chip. Our method is applicable to any power gated design, no matter the side effects (e.g., in timing of events across the interfaces) caused by the particular implementation of power gating.