Abstract
We present in this paper a formal generic framework, implemented in the Coq proof assistant, for defining and reasoning about weak memory models. We first present the three axioms of our framework, with several examples as illustration and justification. Then we show how to implement several existing weak memory models in our framework, and prove formally that our implementation is equivalent to the native definition for each of these models.
Similar content being viewed by others
Notes
By linear order, we mean a relation r that is irreflexive (i.e. ∀x.¬((x,x)∈r)), transitive (i.e. ∀xyz.(x,y)∈r∧(y,z)∈r⇒(x,z)∈r) and total (i.e. ∀xy.(x,y)∈r∨(y,x)∈r).
Note that these are not G. Winskel’s event structures.
We omit the axioms Atomicity and Termination.
References
Sparc Architecture Manual (1992 and 1994) Versions 8 and 9
Power ISA (2009) Version 2.06
Adir A, Attiya H, Shurek G (2003) Information-flow models for shared memory with an application to the powerPC architecture. In: TPDS
Adve SV (1993) Designing memory consistency models for shared-memory multiprocessors. PhD thesis, 1993
Adve SV, Gharachorloo K (1995) Shared memory consistency models: a tutorial. IEEE Comput 29:66–76
Adve SV, Boehm H-J (2012) Memory models: a case for rethinking parallel languages and hardware. Commun ACM. doi:10.1145/1787234.1787255
Ahamad M, Bazzi RA, John R, Kohli P, Neiger G (1993) The power of processor consistency. In: SPAA
Alglave J (2010) A shared memory poetics. PhD thesis, Université Paris 7 and INRIA. http://moscova.inria.fr/~alglave/these
Alglave J, Kroening D, Lugton J, Nimal V, Tautschnig M (2011) Soundness of data flow analyses on weak memory models In: APLAS 11
Alglave J, Maranget L (2011) Stability in weak memory models. In: CAV
Alglave J, Maranget L, Sarkar S, Sewell P (2010) Fences in weak memory models. In: CAV
Alglave J, Maranget L, Sarkar S, Sewell P (2011) Litmus: running tests against hardware. In: TACAS
Alpha Architecture Reference Manual, 4th edn (2002)
Arvind, Maessen J-W (2006) Memory model = instruction reordering + store atomicity. In: ISCA
Bertot Y, Casteran P (2004) Coq’Art, EATCS texts in theoretical computer science. Springer, Berlin
Boehm H-J, Adve SV (2008) Foundations of the C++ concurrency memory model. In: PLDI
Boudol G, Petri G (2009) Relaxed memory models: an operational approach. In: POPL
Burckhardt S, Musuvathi M (2008) Effective program verification for relaxed memory models. In: CAV
Burckhardt S, Musuvathi M, Singh V (2010) Verifying local transformations of concurrent programs. In: CC
Cantin J, Lipasti M, Smith J (2003) The complexity of verifying memory coherence. In: SPAA
Collier WW (1992) Reasoning about parallel architectures. Prentice Hall, New York
Dubois M, Scheurich C (1990) Memory access dependencies in shared-memory multiprocessors. IEEE Trans Softw Eng 16(6). doi:10.1109/32.55094
Ferreira R, Feng X, Shao Z (2010) Parameterized memory models and concurrent separation logic. In: ESOP
Gharachorloo K (1995) Memory consistency models for shared-memory multiprocessors. WRL Res Rep 95(9). doi:10.1.1.37.3026
Hangal S, Vahia D, Manovit C, Lu J-YJ, Narayanan S (2004) TSOTool: a program for verifying memory systems using the memory consistency model. In: ISCA
Higham L, Kawash J, Verwaal N (1998) Weak memory consistency models part I: definitions and comparisons. Technical report 98/612/03, Department of Computer Science, The University of Calgary
Intel 64 Architecture Memory Ordering White Paper, August 2007
Intel 64 and IA-32 Architectures Software Developer’s Manual, vol 3A, October 2011
A Formal Specification of Intel Itanium Processor Family Memory Ordering, October 2002. Intel Document 251429-001
Lamport L (1979) How to make a correct multiprocess program execute correctly on a multiprocessor. IEEE Trans Comput 46(7):779–782
Landin A, Hagersten E, Haridi S (1991) Race-free interconnection networks and multiprocessor consistency. Comput Archit News 19(3):106–115
Manson J, Pugh W, Adve SV (2005) The Java memory model. In: POPL
Owens S, Sarkar S, Sewell P (2009) A better x86 memory model: x86-TSO. In: TPHOL
Sarkar S, Sewell P, Zappa Nardelli F, Owens S, Ridge T, Braibant T, Myreen M, Alglave J (2009) The semantics of x86-CC multiprocessor machine code. In: POPL
Sarkar S, Sewell P, Alglave J, Maranget L, Williams D (2011) Understanding power multiprocessors. In: PLDI 11
Sparc Architecture Manual Version 8 (1992)
Sparc Architecture Manual Version 9 (1994)
Yang Y, Gopalakrishnan G, Lindstrom G (2007) UMM: an operational memory model specification framework with integrated model checking capability. In: CCPE
Yang Y, Gopalakrishnan G, Linstrom G, Slind K (2004) Nemos: a framework for axiomatic and executable specifications of memory consistency models. In: IPDPS
Zappa Nardelli F, Sewell P, Sevcik J, Sarkar S, Owens S, Maranget L, Batty M, Alglave J (2009) Relaxed memory models must be rigorous. In: EC2 09
Acknowledgements
We thank the anonymous reviewers of several versions of this paper for their helpful and insightful reviews. We thank Gérard Boudol, Damien Doligez, Matthew Hague, Maurice Herlihy, Xavier Leroy, Luc Maranget, Susmit Sarkar and Peter Sewell for invaluable discussions and comments, Assia Mahboubi and Vincent Siles for advice on the Coq development, and Thomas Braibant, Matt Lewis, Jules Villard and Boris Yakobowski for comments on a draft.
Author information
Authors and Affiliations
Corresponding author
Appendix: Tables of notations
Appendix: Tables of notations
Rights and permissions
About this article
Cite this article
Alglave, J. A formal hierarchy of weak memory models. Form Methods Syst Des 41, 178–210 (2012). https://doi.org/10.1007/s10703-012-0161-5
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10703-012-0161-5