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The ArchC Architecture Description Language and Tools

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Abstract

This paper presents an architecture description language (ADL) called ArchC, which is an open-source SystemC-based language that is specialized for processor architecture description. Its main goal is to provide enough information, at the right level of abstraction, in order to allow users to explore and verify new architectures, by automatically generating software tools like simulators and co-verification interfaces. ArchC’s key features are a storage-based co-verification mechanism that automatically checks the consistency of a refined ArchC model against a reference (functional) description, memory hierarchy modeling capability, the possibility of integration with other SystemC IPs and the automatic generation of high-level SystemC simulators and assemblers. We have used ArchC to synthesize both functional and cycle-based simulators for the MIPS and Intel 8051 processors, as well as functional models of architectures like SPARC V8, TMS320C62x, XScale and PowerPC.

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Authors and Affiliations

  1. Computer Systems Laboratory, Institute of Computing, University of Campinas, Cidade Universitaria Zeferino Vaz, P.O. Box 6176, Campinas-SP, Brazil

    Rodolfo Azevedo, Sandro Rigo, Marcus Bartholomeu & Guido Araujo

  2. Computer Science Institute, Federal University of Pernambuco, P.O. Box 7851, Recife-PE, Brazil

    Cristiano Araujo & Edna Barros

Authors
  1. Rodolfo Azevedo
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  2. Sandro Rigo
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  3. Marcus Bartholomeu
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  4. Guido Araujo
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  5. Cristiano Araujo
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  6. Edna Barros
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Correspondence to Rodolfo Azevedo.

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Azevedo, R., Rigo, S., Bartholomeu, M. et al. The ArchC Architecture Description Language and Tools. Int J Parallel Prog 33, 453–484 (2005). https://doi.org/10.1007/s10766-005-7301-0

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  • DOI: https://doi.org/10.1007/s10766-005-7301-0

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