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Verification of Embedded Systems Based on Interval Analysis

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Abstract

The latest versions of the “International Technology Roadmap for Semiconductors” (ITRS) highlight that verification has changed from playing a relatively minor supporting role in the design process to becoming the dominant cost. This situation is the result of the exponential growth of the functional complexity of designs and the historical emphasis of CAD tools in other areas of the design process such as automatic synthesis or place-and-route. The problem is even worst in embedded systems that normally integrate functionally complex hardware and software parts. This work presents a new verification technique based on interval analysis that can handle embedded designs described at behavioural level. The proposed technique is able to verify assertions that the users insert in software and hardware tasks. It shows very promising results in systems that cannot be efficiently verified with other tools (e.g. data-dominated designs).

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Authors and Affiliations

  1. Microelectronics Engineering Group, TEISA Department, ETSIIyT, University of Cantabria, Avda, Los Castros, S/n, 39006, Santander, Cantabria, Spain

    Iñigo Ugarte & Pablo Sanchez

Authors
  1. Iñigo Ugarte
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  2. Pablo Sanchez
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Correspondence to Pablo Sanchez.

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Ugarte, I., Sanchez, P. Verification of Embedded Systems Based on Interval Analysis. Int J Parallel Prog 33, 697–720 (2005). https://doi.org/10.1007/s10766-005-8909-9

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  • DOI: https://doi.org/10.1007/s10766-005-8909-9

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