Abstract
Modular exponentiation is a basic operation in various applications, such as cryptography. Generally, the performance of this operation has a tremendous impact on the efficiency of the whole application. Therefore, many researchers have devoted special interest to providing smart methods and efficient implementations for modular exponentiation. One of these methods is the sliding-window method, which pre- processes the exponent into zero and non-zero partitions. Zero partitions allow for a reduction of the number of modular multiplications required in the exponentiation process. In this paper, we devise a novel hardware for computing modular exponentiation using the sliding-window method. The partitioning strategy used allows variable-length non-zero partitions, which increases the average number of zero partitions and so decreases that of non-zero partitions. It performs the partitioning process in parallel with the pre-computation step of the exponent so no overhead is introduced. The implementation is efficient when compared against related existing hardware implementations.
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References
Koç, Ç. K.: High-speed rsa Implementation. Technical Report. RSA Laboratories, Redwood City (1994)
Knuth D.: The Art of Programming: Semi-numerical Algorithms, vol. 2, 2nd edn. Addison- Wesley, Reading (1981)
Kunihiro N., Yamamoto H.: New methods for generating short addition chain. IEICE Trans. E83-A(1), 60–67 (2000)
Menezes A., Oorschot P.V., Vanstone S.: Handbook of Applied Cryptography. CRC Press, USA (1996)
Montgomery P.L.: Modular multiplication without trial division. Math. Comput. 44, 519–521 (1985)
Navabi Z: VHDL—Analysis and Modeling of Digital Systems, 2nd edn. McGraw Hill, USA (1998)
Nedjah, N., Mourelle, L.M.: Four hardware implementations for the m-ary modular exponentiation. In: Proceedings of 3rd International Conference on Information Technology: New Generations, pp. 210–215. IEEE Computer Society, Las Vegas (2006)
Nedjah N., Mourelle L.M.: Hardware architecture for booth-barrett’s modular multiplications. Int. J. Model. Simul. 26(3), 1–8 (2006)
Nedjah N., Mourelle L.M.: Three hardware architectures for the binary modular exponentiation: sequential, parallel and systolic. IEEE Trans. Circuits Syst. I: Fundam. Theory Appl. 53(3), 627–633 (2006)
Nedjah N., Mourelle L.M.: Co-design for System Acceleration: A Quantitative Approach. Springer (former Kluwer Academics), Netherlands (2007)
Nedjah N., Mourelle L.M.: Efficient and secure cryptographic systems based on addition chains: hardware design vs. software/hardware co-design. Integration, the VLSI J. Elsevier 40(1), 36–44 (2007)
Nedjah N., Mourelle L.M.: Fast hardware for modular exponentiation with efficient exponent pre-processing. J. Syst. Archit. 53(2–3), 99–108 (2007)
Nedjah N., Mourelle L.M.: Parallel computation of modular exponentiation for fast cryptography. Int. J. High Perform. Syst. Archit. 1(1), 44–49 (2007)
Nedjah, N., Mourelle, L.M., da Silva, R.: Efficient hardware for modular exponentiation using the sliding-window method. In: Proceedigs of 4th International Conference on Information Technology: New Generations, pp. 17–24. IEEE Computer Society, Las Vegas (2007)
Rivest R., Shamir A., Adleman L.: A method for obtaining digital signature and public-key cryptosystems. Commun. ACM 21, 120–126 (1978)
Silva R.M., Nedjah N., Mourelle L.M.: Efficient hardware for modular exponentiation using the sliding-window method. Int. J. High Perform. Syst. Archit. 1(3), 199–206 (2008)
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Nedjah, N., de Macedo Mourelle, L. High-Performance Hardware of the Sliding-Window Method for Parallel Computation of Modular Exponentiations. Int J Parallel Prog 37, 537–555 (2009). https://doi.org/10.1007/s10766-009-0108-7
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DOI: https://doi.org/10.1007/s10766-009-0108-7