Improved design debugging architecture using low power serial communication protocols for signal processing applications

Abstract

Now-a-days FPGA designers are facing the problem of unprecedented challenges in debugging their designs. In the past, designers debugged their FPGAs by plugging them onto a board and then analyzing them with probes and logic analyzers. But right now the vendors of FPGA are offering tools that make it somewhat easier to probe internal design signals inside the FPGA, Once unexpected behavior is observed, on-chip debug is notoriously difficult; typically a design is instrumented with on-chip trace buffers that record the run-time behavior for later interrogation. Based on the demand for verification leads to an increase in FPGA-based tools that improves the performance of the architecture. The low power communication protocols can run at much higher operating frequencies with less area.FPGAs provide a promising implementation option for many DSP applications particularly in speech signal processing devices such as data converters, digital filters, etc. This work improves the performance of current debugging techniques and makes them more reliable. This work proposes a novel design debugging architecture based on implementation of reconfigurable insertion technique with the help of low power communication protocols used in the FIR filter to debug the entire architecture with less area. If there is any possibility of bug occurs in the UART protocol then the data is transferred through SPI protocol. SPI protocol worked in the operating frequency of 330.12 MHz. According to the power consumption, the UART protocol consumes 0.0135W which is far better than other protocols like SPI, I2C etc. Moreover, the area overhead is reduced. This is achieved by implementing the extra instrumentation. The design debugging architecture is developed using Verilog HDL and implemented on FPGA with the help of Xilinx ISE tool.