Abstract
The latest SRAM-based FPGA devices are making the development of low-cost, high-performance, re-configurable systems feasible, paving the way for innovative architectures suitable for mission- or safety-critical applications, such as those dominating the space or avionic fields. Unfortunately, SRAM-based FPGAs are extremely sensitive to Single Event Upsets (SEUs) induced by radiation. SEUs may alter the logic value stored in the memory elements the FPGAs embed. A large part of the FPGA memory elements is dedicated to the configuration memory, whose content dictates how the resources inside the FPGA have to be used to implement any given user circuit, SEUs affecting configuration memory cells can be extremely critics. Facing the effects of SEUs through radiation-hardened FPGAs is not cost-effective. Therefore, various fault-tolerant design techniques have been devised for developing dependable solutions, starting from Commercial-Off-The-Shelf (COTS) SRAM-based FPGAs. These techniques present advantages and disadvantages that must be evaluated carefully to exploit them successfully. In this paper we mainly adopted an empirical analysis approach. We evaluated the reliability of a multiplier, a digital FIR filter, and an 8051 microprocessor implemented in SRAM-based FPGA’s, by means of extensive fault-injection experiments, assessing the capability provided by different design techniques of tolerating SEUs within the FPGA configuration memory. Experimental results demonstrate that by combining architecture-level solutions (based on redundancy) with layout-level solutions (based on reliability-oriented place and route) designers may implement reliable re-configurable systems choosing the best solution that minimizes the penalty in terms of area and speed degradation.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
M. Bellato, P. Bernardi, D. Bortolato, A. Candelori, M. Cerchia, A. Paccagnella, M. Rebaudengo, M. Sonza Reorda, M. Violante, and P. Zambolin, “Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-based FPGA,” in IEEE Design Automation and Test in Europe, 2004, pp. 188–193.
P. Bernardi, M. Sonza Reorda, L. Sterpone, and M. Violante, “On the Evaluation of SEUs Sensitiveness in SRAM-based FPGAs,” in 10th IEEE International On-line Testing Symposium, 2004, pp. 115–120.
C. Carmichael, “Triple Module Redundancy Design Techniques for Virtex FPGAs,” in Xilinx Application Notes XAPP197, 2001.
“Correcting Single-Event Upset Through Virtex Partial Reconfiguration,” in Xilinx Application Notes XAPP216, 2000.
E. Fuller, M. Caffrey, P. Blain, C. Carmichael, N. Khalsa, A. Salazar, “Radiation Test Results of the Virtex FPGA and ZBT SRAM for Space Based Reconfigurable Computing,” in MAPLD 1999 Proceedings, C_2, September 1999.
F. Lima Kanstensmidt, G. Neuberger, R. Hentschke, L. Carro, and R. Reis, “Designing Fault-Tolerant Techniques for SRAM-based FPGAs,” in IEEE Design & Test of Computers, Nov–Dec 2004, pp. 552–562.
F.L. Kanstensmidt, L. Sterpone, L. Carro, and M. Sonza Reorda, “On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs,” in Design, Automation and Test in Europe, vol. 2, 2005, pp. 1290–1295.
M. Nikolaidis, “Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies,” in IEEE 17th VLSI Test Symposium, April 1999, pp. 86–94.
E. Normand, “Single Event Upset at Ground Level,” IEEE Transactions on Nuclear Science, vol. 43, no. 6, 2742–2750, 1996 (Dec.).
M. Ohlsson, P. Dyreklev, K. Johansson, and P. Afke, “Neutron Single Event Upsets in SRAM-based FPGAs,” in Radiation Effects and Data Workshop, 1998, pp. 177–180.
J. Rose, A. El Gamal, and A. Sangiovanni-Vincetelli, “Architecture of Field-Programmable Gate Arrays,” IEEE Procedings, vol. 81, no. 7, pp. 1013–1029, 1993 (July).
S Habinc Gaisler Research, “Functional Triple Modular Redundancy (FTMR) VHDL Design Methodology for Redundancy in Combinational and Sequential logic,” www.gaisler.com.
P.K. Samudrala, J. Ramos, and S. Katkoori, “Selective Triple Modular Redundancy (STMR) Based Single-Event Upset (SEU) Tolerant Synthesis for FPGAs,” IEEE Transactions on Nuclear Science, vol. 51, no. 5, pp. 2957–2969, 2004 (Oct.).
M. Sonza Reorda, L. Sterpone, and M. Violante, “Multiple Errors Provoked by SEUs in the FPGA Configuration Memory: A Possible Solution,” in 10th IEEE European Test Symposium, 2005, pp. 136–141.
“Spartan-II 2.5 V FPGA family: Introduction and Ordering Information,” in Xilinx Product Specification Datasheets, 2003.
C. Stroud, J. Nall, M. Lashinsky, and M. Abramovici, “BIST-Based Diagnosis of FPGA Interconnect,” in Proceedings of the IEEE International Test Conference, 2002, pp. 618–627.
“TMRTool User Guide,” in Xilinx User Guide UG156, 2004.
“Virtex 2.5 FPGA family: Introduction and Ordering Information,” in Xilinx Product Specification Datasheets, 2001.
M. Wirthlin, E. Johnson, N. Rollins, M. Caffrey, and P. Graham, “The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets,” in Proc. 11th Ann. IEEE Symposium on Field-Programmable Custom Computing Machines, 2003, pp. 133–142.
Author information
Authors and Affiliations
Corresponding author
Additional information
Editor: C. E. Stroud
Rights and permissions
About this article
Cite this article
Sterpone, L., Sonza Reorda, M., Violante, M. et al. Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. J Electron Test 23, 47–54 (2007). https://doi.org/10.1007/s10836-006-0403-9
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-006-0403-9