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Scaling of i DDT Test Methods for Random Logic Circuits

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Abstract

We present a scaling methodology to improve i DDT fault coverage in random logic circuits. The study targets two i DDT test methods: Double Threshold i DDT and Delayed i DDT . The effectiveness of the scaling methodology is assessed through physical test measurements, and studied relative to process variation and impact on circuit performance. The scaling is made possible using a clustering methodology that can significantly improve fault coverage. The results show that without clustering, the effectiveness of the i DDT testing methods considered is greatly reduced as the circuit size increases.

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Correspondence to Ali Chehab.

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Editor: Z Li

Ali Chehab received his Bachelor degree in EE from the American University of Beirut (AUB) in 1987, the Master’s degree in EE from Syracuse University, and the PhD degree in ECE from the University of North Carolina at Charlotte, in 2002. From 1989 to 1998, he was a lecturer in the ECE Department at AUB. He rejoined the ECE Department at AUB as an assistant professor in 2002. His research interests are VLSI design and test, mobile agents, and wireless security.

Rafic Makki is currently serving as Dean of the College of Information Technology at UAE University. Rafic began his career with the University of North Carolina at Charlotte in 1984, serving the university for a period of 19 years. Rafic is the recipient of several awards including the 2005 IBM Faculty Research Award (first in the Middle-East), the 2002 First Citizen Research Scholar Medal, and the ALCOA Outstanding Graduate Faculty Award. Rafic received a PhD in Electrical Engineering in 1983 from Tennessee Tech University. His research interests include design for testability and defect-based testing.

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Chehab, A., Patel, S. & Makki, R. Scaling of i DDT Test Methods for Random Logic Circuits. J Electron Test 22, 11–22 (2006). https://doi.org/10.1007/s10836-006-4835-z

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  • DOI: https://doi.org/10.1007/s10836-006-4835-z

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