This is a preview of subscription content, log in via an institution to check access.
Additional information
Bashir M. Al-Hashimi received the BSc degree with First Class in Electrical and Electronics Engineering from the University of Bath, UK, and the PhD degree from York University, UK. Following those he worked in the semiconductor industry designing integrated circuits for signal processing applications, developing CAD tools for simulation and synthesis of analogue and digital circuits. In 1999, he joined the School of Electronics and Computer Science, Southampton University, UK, where he is currently a Professor of Computer Engineering. He has authored one book on SPICE simulation (CRC Press, 1995), and coauthored two books, Power Constrained Testing of VLSI circuits (Springer, 2002), and System-Level Design Techniques for Energy-Efficient Embedded Systems(Springer, 2004). Recently, he edited the book, System-on-Chip: Next Generation Electronics(IEE Press, 2006). He has authored and coauthored over 150 technical papers. His research and teaching interests include low-power system-level design, system-on-chip test, and VLSI CAD. He is the Editor-in-Chief of the IEE Proceedings: Computers and Digital Techniques. He is a Fellow of the IEE. He is the General Chair of the 11th IEEE European Test Symposium (Southampton 2006) and the General Chair of DATE Friday Workshops (2005 and 2006). He was the co-author of the James Beausang Best Paper Award at the 2000 IEEE International Test Conference relating to low power BIST for RTL data paths.
Dimitris Gizopoulos is an Assistant Professor in the Department of Informatics, University of Piraeus, Greece. He received his PhD from University of Athens (1997) and the Computer Engineering Diploma, from University of Patras (1992). His research interests include test generation, fault modeling, self-testing, and on-line testing of digital systems. Gizopoulos is co-author of one book and editor of another in Springer’s Frontiers in Electronic Testing book series. He has published more than seventy papers in peer reviewed transactions, journals and conference proceedings and holds a patent. He is an editorial board member of the IEEE Design & Test of Computers Magazine, and has been guest co-editor in IEEE publications special issues. He was General Chair of the IEEE European Test Workshop 2002 and the IEEE International On-Line Testing Symposium 2003 and Program Chair of the IEEE International Workshop on Infrastructure IP since 2003. Since 1998, he is member of the Executive Committee of the Test Technology Technical Council with contributions to the Technical Meetings and the Tutorials and Education Groups. He is member of the Steering Committees of ITC and ETS and the Program and Organizing Committees of several technical meetings. He is a senior member of IEEE and a Golden Core member of the IEEE Computer Society.
Manoj Sachdev is a Professor in the Electrical and Computer Engineering Department at University of Waterloo, Canada. His research interests include low power and high performance digital circuit design, mixed-signal circuit design, test and manufacturing issues of integrated circuits. He has written two books, two book chapters, and has contributed to 100 technical articles in conferences and journals. He holds more than 15 granted and several pending US patents in the broad area of VLSI circuit design and test. He has received several awards including the 1997 European Design and Test Conference best paper award, the 1998 International Test conference honorable mention award, and the 2004 VLSI Test Syposium best panel award. He is a senior member of IEEE. He received his BE degree (with Honors) in electronics and communication engineering from University of Roorkee (India), and PhD from Brunel University (UK). He was with Semiconductor Complex Limited, Chandigarh (India) from 1984 through 1989 and designed CMOS Integrated Circuits. From 1989 through 1992, he worked at the ASIC division of SGS-Thomson in Agrate (Milan). In 1992, he joined Philips Research Laboratories, Eindhoven, where he researched on various aspects of VLSI testing and manufacturing.
Adit D. Singh received the BTech degree from the Indian Institute of Technology, Kanpur, and the MS and PhD degrees from Virginia Tech, all in Electrical Engineering. Currently he serves as James B. Davis Professor of Electrical and Computer Engineering at Auburn University in Alabama. Earlier, he held faculty positions at the University of Massachusetts, Amherst, and Virginia Tech, Blacksburg. His technical interests span all aspects of VLSI design, test and reliability. He has published over one hundred research papers, and holds international patents that have been licensed to industry. He has held leadership roles at various international conferences, including serving as General Chair of the 2000 IEEE VLSI Test Symposium, the 2003 IEEE Defect Based Test Workshop, and the 2004 IEEE Memory Test Workshop. He currently serves on the editorial board of the IEEE Design and Test of Computers magazine. Dr. Singh has received several honors, including a Fulbright Award for US-Spain collaborative research. He is a Fellow of IEEE and a Golden Core member of the IEEE Computer Society. Currently, he is a Vice Chair of the IEEE Test Technology Technical Council and serves on the Executive Committee of the IEEE Computer Societies Technical Activities Board.
Rights and permissions
About this article
Cite this article
Al-Hashimi, B.M., Gizopoulos, D., Sachdev, M. et al. New JETTA Editors, 2006. J Electron Test 22, 9–10 (2006). https://doi.org/10.1007/s10836-006-6905-7
Issue Date:
DOI: https://doi.org/10.1007/s10836-006-6905-7