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Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations

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Abstract

Scan-based cores impose considerable test power challenges due to excessive switching activity during shift cycles. The consequent test power constraints force system-on-chip (SOC) designers to sacrifice parallelism among core tests, as exceeding power thresholds may damage the chip being tested. Reduction of test power for SOC cores can thus increase the number of cores that can be tested in parallel, improving significantly SOC test application time. In this paper, we propose a scan chain modification technique that inserts logic gates on the scan path. The consequent beneficial test data transformations are utilized to reduce the scan chain transitions during shift cycles and hence test power. We introduce a matrix band algebra that models the impact of logic gate insertion between scan cells on the test stimulus and response transformations realized. As we have successfully modeled the response transformations as well, the methodology we propose is capable of truly minimizing the overall test power. The test vectors and responses are analyzed in an intertwined manner, identifying the best possible scan chain modification, which is realized at minimal area cost. Experimental results justify the efficacy of the proposed methodology as well.

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Notes

  1. A simple transposition argument can be used to show that a lower triangular matrix can be left-multiplied by the stimulus matrix, equivalently. The test stimulus and vector will be denoted in column form in that case.

  2. As these matrix multiplications model XOR operations, the inner products are to be computed through XORing the product terms.

  3. It has been shown in Sankaralingam et al. [20] that the number of scan chain transitions and the actual test power dissipation are strongly correlated.

  4. The techniques in Sinanoglu et al. [29] and Sinanoglu and Orailoglu [27] are based on minimizing scan-in power; the associated papers therefore report scan-in power reduction. In this paper, the results of these techniques that are reported in Table 3 are computed by also accounting for the scan-out power, yielding different results than those reported in these papers.

  5. For a fair comparison, we have implemented the repeat-fill approach and used the same set of test cubes, generated by ATALANTA, for both the repeat-fill and the proposed techniques; it must be noted however that the proposed methodology attains power reductions without exploiting any don’t care bits. In other words, the proposed methodology is executed on a fully specified test set, with no don’t care bits whatsoever, which has been generated from the test cubes via random-fill.

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Acknowledgment

The author would like to thank Prof. Irith Pomeranz, from Purdue University, for providing on a short notice the test data for the enhanced COMPACTEST tool.

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  1. Mathematics and Computer Science Department, Kuwait University, Safat, Kuwait

    Ozgur Sinanoglu

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  1. Ozgur Sinanoglu
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Correspondence to Ozgur Sinanoglu.

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Responsible Editor: B. Al-Hashimi

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Sinanoglu, O. Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations. J Electron Test 24, 335–351 (2008). https://doi.org/10.1007/s10836-007-5021-7

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