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A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique

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Abstract

Some asynchronous circuit techniques are proposed to provide a new approach to Single Event Effect (SEE) tolerance in synchronous circuits. Two structures, Double Modular Redundancy (DMR) and Temporal Spatial Triple Modular Redundancy with Dual Clock Triggered Register (TSTMR-D), are presented. Three SEE tolerant 8051 cores with DMR, TSTMR-D and traditional Triple Modular Redundancy (TMR) are implemented in SMIC 0.35 μm process. The results of fault injection experiments indicate that DMR has a relatively low overhead on both area and latency than TMR, while tolerates SEU in sequential logic. TSTMR-D provides tolerance for both SEU and SET with reasonable area and latency overhead.

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Authors and Affiliations

  1. School of Computer, National University of Defense Technology, Changsha, 410073, PR China

    Rui Gong, Wei Chen, Fang Liu, Kui Dai & Zhiying Wang

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  1. Rui Gong
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  2. Wei Chen
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  3. Fang Liu
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  4. Kui Dai
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  5. Zhiying Wang
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Corresponding author

Correspondence to Rui Gong.

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Responsible Editor: N. A. Touba

This work is supported by the National Natural Science Foundation of China under grant No. 90407022.

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Gong, R., Chen, W., Liu, F. et al. A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique. J Electron Test 24, 57–65 (2008). https://doi.org/10.1007/s10836-007-5029-z

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  • DOI: https://doi.org/10.1007/s10836-007-5029-z

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