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A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis

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Abstract

This paper reports a case study on the automatic layout generation and transient fault injection analysis of a Phase-Locked Loop (PLL). A script methodology was used to generate the layout based on transistor level specifications. Experiences were performed in the PLL in order to evaluate the sensibility against transient faults. The circuit was generated using the STMicroelectronics HCMOS8D process (0.18 μm). Results reveal the PLL sensitive points allowing the study and development of techniques to protect this circuit against transient faults.

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Authors and Affiliations

  1. PGMICRO, UFRGS, Porto Alegre, Brazil

    Cristiano Lazzari

  2. PGMICRO/PPGC, Instituto de Informática, UFRGS, Porto Alegre, Brazil

    Ricardo A. L. Reis

  3. TIMA Laboratory, INPG, Grenoble, France

    Lorena Anghel

Authors
  1. Cristiano Lazzari
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  2. Ricardo A. L. Reis
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  3. Lorena Anghel
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Corresponding author

Correspondence to Cristiano Lazzari.

Additional information

Responsible Editor: M. Lubaszewski

Supported by CAPES Brazilian Research Agency.

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Lazzari, C., Reis, R.A.L. & Anghel, L. A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis. J Electron Test 23, 625–633 (2007). https://doi.org/10.1007/s10836-007-5055-x

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  • DOI: https://doi.org/10.1007/s10836-007-5055-x

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